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    THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME
    41.
    发明公开
    THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240015974A1

    公开(公告)日：2024-01-11

    申请号：US17857264

    申请日：2022-07-05

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Linchun WU ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

    IPC: H01L27/11575 ,  H01L23/535 ,  H01L27/11582

    CPC classification number: H01L27/11575 ,  H01L23/535 ,  H01L27/11582

    Abstract: A semiconductor device semiconductor device includes a stack having a first surface and a second surface opposing the first surface. The stack can include word line layers and insulating layers alternating with the word line layers between the first surface and the second surface. The stack can further include a process stop layer between the lower most insulating layer and the second surface. The stack can extend along an X-Y plane having an X direction and a Y direction perpendicular. The semiconductor device can further include a slit structure crossing the stack between the first surface and the second surface in Z direction. In a cross-section perpendicular to the Y direction, distances between the slit structure and the process stop layer at two sides of the slit structure are each larger than distances at either side of the slit structure between the word line layers and the slit structure.

    VERTICAL MEMORY DEVICES AND METHOD OF FABRICATION THEREOF
    42.
    发明公开
    VERTICAL MEMORY DEVICES AND METHOD OF FABRICATION THEREOF 审中-公开

    公开(公告)号：US20230420372A1

    公开(公告)日：2023-12-28

    申请号：US17848008

    申请日：2022-06-23

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Jingtao XIE ,  Bingjie YAN ,  Wenxi ZHOU ,  Di WANG ,  Zhiliang XIA ,  Zongliang HUO

    IPC: H01L23/535 ,  H01L27/11582

    CPC classification number: H01L23/535 ,  H01L27/11582

    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack structure and a contact structure. The stack structure comprises interleaved gate layers and insulating layers. The contact structure comprises a conductive structure and one or more insulating structures. The conductive structure can extend through the stack structure and form a conductive connection with one of the gate layers. The one or more insulating structures surround the conductive structure and electrically isolate the conductive structure from remaining ones of the gate layers. The one or more insulating structures further include one or more first insulating structures. Each of the one or more first insulating structures is disposed between an adjacent pair of the insulating layers, and the one or more first insulating structures are disposed on a first side of the one of the gate layers.

    METHOD AND APPARATUS FOR DATA ERASE IN MEMORY DEVICES
    45.
    发明申请
    METHOD AND APPARATUS FOR DATA ERASE IN MEMORY DEVICES 有权

    公开(公告)号：US20220351781A1

    公开(公告)日：2022-11-03

    申请号：US17866999

    申请日：2022-07-18

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

    IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

    Abstract: Aspects of the disclosure provide an erase method for a memory device. In the method, during a time period, a first positive voltage is applied to a body portion of a memory cell string of the memory device. The memory cell string includes memory cell transistors and select transistors connected in series. A second positive voltage is applied to a bit line signal of the memory cell string. A third positive voltage is applied to a first top select gate signal to turn on a first top select transistor of the select transistors so that the memory cell transistors are coupled to the bit line signal through the first top select transistor. A ground level voltage or a fourth positive voltage is applied to a word line signal of the memory cell transistors. Both the third and fourth positive voltages are less than the second positive voltage.

    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY DEVICE
    46.
    发明申请
    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY DEVICE 有权

    公开(公告)号：US20210265375A1

    公开(公告)日：2021-08-26

    申请号：US17313740

    申请日：2021-05-06

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Zhongwang SUN ,  Guangji LI ,  Kun ZHANG ,  Ming HU ,  Jiwei CHENG ,  Shijin LUO ,  Kun BAO ,  Zhiliang XIA

    IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

    Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

    VERTICAL MEMORY DEVICES
    47.
    发明申请
    VERTICAL MEMORY DEVICES 有权

    公开(公告)号：US20210257386A1

    公开(公告)日：2021-08-19

    申请号：US17246750

    申请日：2021-05-03

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Di WANG ,  Rui SU ,  Zhongwang SUN ,  Zhiliang XIA ,  Wenxi ZHOU

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first stack of layers including a source connection layer and a second stack of layers including gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatively upon the first stack of layers. Further, the semiconductor device includes channel structures that are formed along the first direction in the first stack of layers and the second stack of layers, and a gate line cut structure having a trench that cuts through the first stack of layers and the second stack of layers. The trench is filled with at least an insulating layer. The semiconductor device includes a support structure having a first portion that is disposed at a side of the gate line cut structure and extended from the side of the gate line cut structure and underneath the second stack of layers.

    VERTICAL MEMORY DEVICES
    48.
    发明申请
    VERTICAL MEMORY DEVICES 有权

    公开(公告)号：US20210233870A1

    公开(公告)日：2021-07-29

    申请号：US17113442

    申请日：2020-12-07

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Yuhui HAN ,  Zhiliang XIA ,  Wenxi ZHOU

    IPC: H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

    Abstract: A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

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