公开(公告)号：US20060176145A1

公开(公告)日：2006-08-10

申请号：US11053636

申请日：2005-02-07

Applicant: Yongki Min ,  Chien Yu

Inventor： Yongki Min ,  Chien Yu

IPC: H01C1/012

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01C17/08 ,  H05K1/0263 ,  H05K1/167 ,  H05K2201/0317 ,  H05K2203/1461

Abstract: A substrate that includes an embedded thin-film resistor coupled to one or more relatively thick conductive traces, and its application, are described herein.

Abstract translation: 本文描述了包括耦合到一个或多个相对厚的导电迹线的嵌入式薄膜电阻器及其应用的衬底。

公开(公告)号：US20060099803A1

公开(公告)日：2006-05-11

申请号：US10974139

申请日：2004-10-26

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L21/4763

CPC classification number: H01G4/30 ,  H01G4/0085 ,  H01G4/232 ,  H01L2224/16225

Abstract: A method including forming a barrier material on a surface of an electrode of a capacitor structure; forming a ceramic material on the electrode material; and annealing the ceramic material, wherein the barrier material comprises a material having a property that inhibits the oxidation of a material for the electrode during annealing of the ceramic material. An apparatus including a first electrode; a second electrode; a ceramic material disposed between the first electrode and the second electrode; and a barrier material between the ceramic material and at least one of the first electrode and the second electrode. A method including forming a ceramic material on a surface of an electrode of a capacitor structure; and annealing the ceramic material through a rapid thermal anneal process.

Abstract translation: 一种包括在电容器结构的电极的表面上形成阻挡材料的方法; 在电极材料上形成陶瓷材料; 以及退火所述陶瓷材料，其中所述阻挡材料包括具有在所述陶瓷材料退火期间抑制所述电极材料的氧化性能的材料。 一种装置，包括：第一电极; 第二电极; 设置在所述第一电极和所述第二电极之间的陶瓷材料; 以及陶瓷材料和第一电极和第二电极中的至少一个之间的阻挡材料。 一种包括在电容器结构的电极的表面上形成陶瓷材料的方法; 并通过快速热退火工艺退火陶瓷材料。

公开(公告)号：US20060091495A1

公开(公告)日：2006-05-04

申请号：US10976425

申请日：2004-10-29

Applicant: Cengiz Palanduz ,  Yongki Min

Inventor： Cengiz Palanduz ,  Yongki Min

IPC: H01L29/00

CPC classification number: H01L23/50 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/388 ,  H05K2203/0315 ,  H01L2224/0401

Abstract: A method including forming a first metal material layer on a dielectric material; transitioning a portion of the first metal material adjacent to the dielectric to a first oxidation state and a portion of the metal material peripheral to the dielectric material to a second different oxidation state; and forming a second metal material layer on the first metal material. An apparatus including an interposer substrate including an adhesion layer including a metal material having respective portions including at least two different oxidation states; and a capacitor on the adhesion layer. A system including a computing device including a microprocessor, the microprocessor coupled to a printed circuit board through an interposer including an interposer substrate, a capacitor, and an adhesion layer between the interposer substrate and the capacitor, the adhesion layer including a metal material having respective portions including at least two different oxidation states.

Abstract translation: 一种包括在电介质材料上形成第一金属材料层的方法; 使与电介质相邻的第一金属材料的一部分转变为第一氧化态，并将该电介质材料周边的金属材料的一部分转变为第二不同的氧化态; 以及在所述第一金属材料上形成第二金属材料层。 一种包括内插衬底的装置，包括具有包含至少两种不同氧化态的各部分的金属材料的粘合层; 和粘附层上的电容器。 一种包括计算设备的系统，包括微处理器，所述微处理器通过内插器耦合到印刷电路板，所述插入器包括插入器基板，电容器和所述插入器基板与所述电容器之间的粘附层，所述粘合层包括具有相应的金属材料 部分包括至少两种不同的氧化态。

公开(公告)号：US20060000542A1

公开(公告)日：2006-01-05

申请号：US10882745

申请日：2004-06-30

Applicant: Yongki Min ,  Cengiz Palanduz

Inventor： Yongki Min ,  Cengiz Palanduz

IPC: C03B29/00

CPC classification number: H01G4/1227 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/162 ,  H05K2201/017 ,  H05K2201/0355

Abstract: A method including forming a capacitor structure including an electrode material and a ceramic material on the electrode material; and sintering the ceramic material under a condition where a point defect state of the ceramic material defines the ceramic material as insulating without oxidation of the electrode material. A method including depositing a ceramic material on an electrically conductive foil; and sintering the ceramic material in a reducing atmosphere at a temperature that minimizes the mobility of point defects to transition to a level corresponding to a greater conductivity of the ceramic material. An apparatus including a first electrode; a second electrode; and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material includes a thickness less than one micron and a leakage current corresponding to a thermodynamic state wherein a concentration of mobile point defects have been optimized.

Abstract translation: 一种包括在电极材料上形成包括电极材料和陶瓷材料的电容器结构的方法; 并且在陶瓷材料的点缺陷状态将陶瓷材料定义为绝缘而不氧化电极材料的条件下烧结陶瓷材料。 一种方法，包括在导电箔上沉积陶瓷材料; 以及在使缺陷的迁移率最小化以转变到对应于陶瓷材料的更大导电率的水平的温度下，在还原气氛中烧结陶瓷材料。 一种装置，包括：第一电极; 第二电极; 以及设置在所述第一电极和所述第二电极之间的陶瓷材料，其中所述陶瓷材料包括小于1微米的厚度和对应于已经优化了移动点缺陷的浓度的热力学状态的泄漏电流。

公开(公告)号：US08618593B2

公开(公告)日：2013-12-31

申请号：US13214773

申请日：2011-08-22

Applicant: Islam A. Salama ,  Yongki Min

Inventor： Islam A. Salama ,  Yongki Min

IPC: H01L27/108 ,  H01L29/94 ,  H01L21/02

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2203/1105

Abstract: Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括形成在集成电路封装的封装衬底上的薄膜电容器。 薄膜电容器中的至少一个包括在第一和第二电极层之间的第一电极层，第二电极层和电介质层。 第一和第二电极层和电介质层中的每一个单独形成并直接形成在封装衬底上。 描述和要求保护其他实施例。

公开(公告)号：US08228680B2

公开(公告)日：2012-07-24

申请号：US12699939

申请日：2010-02-04

Applicant: Myitzu Soe Myat ,  Mooi Ling Chang ,  Eu Soon Lee ,  Yongki Min ,  King Keong Wong

Inventor： Myitzu Soe Myat ,  Mooi Ling Chang ,  Eu Soon Lee ,  Yongki Min ,  King Keong Wong

IPC: H05K1/16

CPC classification number: H01L23/5223 ,  H01L23/50 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/023 ,  H01L2924/00

Abstract: Using die side capacitors and embedded resistors, an advantageous power delivery network may be achieved. In some embodiments, the embedded resistors may be more precisely controllable. The number of die side capacitors may be reduced by combining embedded resistors with these capacitors to reduce costs. The embedded resistors may be provided within the metallization layers either at an upper layer or a lower layer, as two examples.

Abstract translation: 使用裸片侧电容器和嵌入式电阻器，可以实现有利的电力输送网络。 在一些实施例中，嵌入式电阻器可以更精确地可控制。 可以通过将嵌入式电阻器与这些电容器组合来降低芯片侧电容器的数量，以降低成本。 作为两个实例，嵌入式电阻器可以在上层或下层设置在金属化层内。

公开(公告)号：US08143697B2

公开(公告)日：2012-03-27

申请号：US12501306

申请日：2009-07-10

Applicant: Huankiat Seh ,  Yongki Min

Inventor： Huankiat Seh ,  Yongki Min

IPC: H01L23/522 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15313 ,  H05K1/112 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2203/102 ,  H05K2203/1105

Abstract: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括形成在集成电路封装的封装衬底中的薄膜电容器。 薄膜电容器中的至少一个包括在第一和第二电极层之间的第一电极层，第二电极层和电介质层。 第一和第二电极层和电介质层中的每一个单独形成并直接形成在封装衬底上。 描述和要求保护其他实施例。

公开(公告)号：US20090273057A1

公开(公告)日：2009-11-05

申请号：US12501306

申请日：2009-07-10

Applicant: Huankiat Seh ,  Yongki Min

Inventor： Huankiat Seh ,  Yongki Min

IPC: H01L29/92

CPC classification number: H05K1/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15313 ,  H05K1/112 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2203/102 ,  H05K2203/1105

Abstract: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括形成在集成电路封装的封装衬底中的薄膜电容器。 薄膜电容器中的至少一个包括在第一和第二电极层之间的第一电极层，第二电极层和电介质层。 第一和第二电极层和电介质层中的每一个单独形成并直接形成在封装衬底上。 描述和要求保护其他实施例。

公开(公告)号：US07588992B2

公开(公告)日：2009-09-15

申请号：US11152328

申请日：2005-06-14

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L21/461

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2203/0384 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A thin-film capacitor assembly includes a first metal bottom electrode, a dielectric layer, a second metal etch-stop layer, and a subsequent metal top electrode. The first metal bottom electrode is in contact with the dielectric layer. The second metal etch-stop layer is in contact with the dielectric layer. The subsequent metal top electrode is in contact with the second metal etch-stop layer. Processing of the thin-film capacitor assembly includes totally removing a stiffener after assembling the first metal bottom electrode as a layer to the dielectric layer and the second metal etch-stop layer. The stiffener is removed from above and on the second metal etch-stop layer. The thin-film capacitor assembly is laminated to a mounting substrate.

Abstract translation: 薄膜电容器组件包括第一金属底电极，电介质层，第二金属蚀刻停止层和随后的金属顶电极。 第一金属底电极与电介质层接触。 第二金属蚀刻停止层与电介质层接触。 随后的金属顶电极与第二金属蚀刻停止层接触。 薄膜电容器组件的处理包括在将第一金属底电极组装成介电层和第二金属蚀刻停止层之后，完全去除加强件。 加强件从第二金属蚀刻停止层上方和第二金属蚀刻停止层移除。 将薄膜电容器组件层压到安装基板上。

公开(公告)号：US07553738B2

公开(公告)日：2009-06-30

申请号：US11609295

申请日：2006-12-11

Applicant: Yongki Min ,  Huankiat Seh

Inventor： Yongki Min ,  Huankiat Seh

IPC: H01L21/20

CPC classification number: H01G4/33 ,  H01G4/232 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L27/016 ,  H01L2924/0002 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/1184 ,  Y10S438/957 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/43 ,  H01L2924/00

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer. The passive microelectronic structure being embedded includes an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer.

Abstract translation: 微电子器件，制造该器件的方法以及包括该器件的系统。 该方法包括：提供包括下面的导电层和覆盖在下面的导电层上的聚合物堆积层的衬底; 提供无源微电子结构; 将被动结构嵌入衬底的聚合物堆积层中; 并且在嵌入之后图案化被动结构，图案化包括对底部电极层进行过蚀刻。 嵌入的被动微电子结构包括未图案化的底电极层; 覆盖底部电极层的未图案化的电容器电介质层; 以及覆盖电容器介电层的未图案化的顶部电极层。