公开(公告)号：US08623737B2

公开(公告)日：2014-01-07

申请号：US11396386

申请日：2006-03-31

Applicant: Huankiat Seh ,  Yongki Min ,  Cengiz A. Palanduz

Inventor： Huankiat Seh ,  Yongki Min ,  Cengiz A. Palanduz

IPC: H01L21/20

CPC classification number: G06F1/1601 ,  H01G4/12 ,  H01G4/33 ,  H01L23/50 ,  H01L27/0805 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  Y10T29/435 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A process of forming a thin-film capacitor that includes sol-gel patterning of a dielectric thin film on a first electrode, lift-off removal of unwanted dielectric thin film, and mating the dielectric thin film with a second electrode. The thin-film capacitor exhibits a substantially uniform heat-altered morphology along a line defined by a characteristic dimension thereof. A computing system is also disclosed that includes the thin-film capacitor.

Abstract translation: 一种形成薄膜电容器的方法，该薄膜电容器包括在第一电极上的电介质薄膜的溶胶凝胶图案化，去除不想要的电介质薄膜的剥离以及使第二电极与电介质薄膜匹配。 薄膜电容器沿着由其特征尺寸限定的线显示出基本均匀的热改变的形态。 还公开了包括薄膜电容器的计算系统。

公开(公告)号：US08003479B2

公开(公告)日：2011-08-23

申请号：US11277606

申请日：2006-03-27

Applicant: Islam A. Salama ,  Yongki Min

Inventor： Islam A. Salama ,  Yongki Min

IPC: H01L21/20

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2203/1105

Abstract: Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括形成在集成电路封装的封装衬底上的薄膜电容器。 薄膜电容器中的至少一个包括在第一和第二电极层之间的第一电极层，第二电极层和电介质层。 第一和第二电极层和电介质层中的每一个单独形成并直接形成在封装衬底上。 描述和要求保护其他实施例。

公开(公告)号：US20110034002A1

公开(公告)日：2011-02-10

申请号：US12908317

申请日：2010-10-20

Applicant: Huankiat Seh ,  Yongki Min ,  Islam A. Salama

Inventor： Huankiat Seh ,  Yongki Min ,  Islam A. Salama

IPC: H01L21/02

CPC classification number: H05K1/185 ,  H01L23/50 ,  H01L23/642 ,  H01L24/97 ,  H01L25/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H05K1/023 ,  H05K1/183 ,  H05K3/0032 ,  H05K3/0052 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49146

Abstract: A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plurality of separated non-removed portions, and curing the separated non-removed portions of the dielectric layer.

Abstract translation: 一种方法可以包括将电介质层沉积到衬底上，去除电介质层的部分以产生电介质层的多个分离的未除去部分，将一个或多个无源电子元件沉积到多个分离的未除去的每一个中 部分，并且固化电介质层的分离的未除去部分。

公开(公告)号：US07838419B2

公开(公告)日：2010-11-23

申请号：US11642350

申请日：2006-12-20

Applicant: Huankiat Seh ,  Yongki Min ,  Islam A. Salama

Inventor： Huankiat Seh ,  Yongki Min ,  Islam A. Salama

IPC: H01L21/44

CPC classification number: H05K1/185 ,  H01L23/50 ,  H01L23/642 ,  H01L24/97 ,  H01L25/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H05K1/023 ,  H05K1/183 ,  H05K3/0032 ,  H05K3/0052 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49146

Abstract: A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plurality of separated non-removed portions, and curing the separated non-removed portions of the dielectric layer.

Abstract translation: 一种方法可以包括将电介质层沉积到衬底上，去除电介质层的部分以产生电介质层的多个分离的未除去部分，将一个或多个无源电子元件沉积到多个分离的未除去的每一个中 部分，并且固化电介质层的分离的未除去部分。

公开(公告)号：US07738257B2

公开(公告)日：2010-06-15

申请号：US11610385

申请日：2006-12-13

Applicant: Islam Salama ,  Yongki Min ,  Huankiat Seh

Inventor： Islam Salama ,  Yongki Min ,  Huankiat Seh

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09718 ,  H05K2201/09918 ,  H05K2203/0353 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The device includes: a substrate including a polymer build-up layer, and a passive structure embedded in the substrate. The passive structure includes a top conductive layer overlying the polymer build-up layer, a dielectric layer overlying the top conductive layer, and a bottom conductive layer overlying the dielectric layer. The device further includes a conductive via extending through the polymer build-up layer and electrically insulated from the bottom conductive layer, an insulation material insulating the conductive via from the bottom conductive layer, and a bridging interconnect disposed at a side of the top conductive layer facing away from the dielectric layer, the bridging interconnect electrically connecting the conductive via to the top conductive layer.

Abstract translation: 微电子器件，制造该器件的方法以及包括该器件的系统。 该装置包括：包含聚合物累积层的基底和嵌入基底中的被动结构。 被动结构包括覆盖聚合物积聚层的顶部导电层，覆盖顶部导电层的电介质层和覆盖在电介质层上的底部导电层。 该器件还包括延伸穿过聚合物积聚层并与底部导电层电绝缘的导电通孔，将导电通孔与底部导电层绝缘的绝缘材料以及布置在顶部导电层侧面的桥接互连 背离电介质层，桥接互连将导电通孔电连接到顶部导电层。

公开(公告)号：US07402909B2

公开(公告)日：2008-07-22

申请号：US11116537

申请日：2005-04-28

Applicant: Daewoong Suh ,  Amram Eitan ,  Yongki Min

Inventor： Daewoong Suh ,  Amram Eitan ,  Yongki Min

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49827 ,  B82Y10/00 ,  C09J7/22 ,  C09J9/02 ,  C09J2201/128 ,  C09J2201/602 ,  C09J2203/326 ,  H01L23/49877 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/11452 ,  H01L2224/1182 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13193 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13666 ,  H01L2224/16145 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/29 ,  H01L2224/29076 ,  H01L2224/29078 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83203 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H05K3/323 ,  H05K2201/026 ,  Y10S977/848 ,  Y10S977/932 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.

Abstract translation: 提供互连和互连的方法来连接集成电路的第一部件和第二部件。 互连包括多个碳纳米管（CNT），其在第一部件和第二部件之间提供导电路径。 互连还包括钝化层以填充相邻CNT之间的间隙。 提供制造各向异性导电膜（ACF）和ACF的方法。 ACF包括多个CNT，其在ACF的第一侧和ACF的第二侧之间提供导电路径。 ACF的侧面还可以包括导电的可固化粘合剂层。 在一个实施方案中，导电可固化粘合剂层可以并入B级可交联聚合物和银颗粒。

公开(公告)号：US20080003765A1

公开(公告)日：2008-01-03

申请号：US11427532

申请日：2006-06-29

Applicant: Huankiat Seh ,  Yongki Min

Inventor： Huankiat Seh ,  Yongki Min

IPC: H01L21/20

CPC classification number: H05K1/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15313 ,  H05K1/112 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2203/102 ,  H05K2203/1105

Abstract: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括形成在集成电路封装的封装衬底中的薄膜电容器。 薄膜电容器中的至少一个包括在第一和第二电极层之间的第一电极层，第二电极层和电介质层。 第一和第二电极层和电介质层中的每一个单独形成并直接形成在封装衬底上。 描述和要求保护其他实施例。

公开(公告)号：US20070271752A1

公开(公告)日：2007-11-29

申请号：US11891443

申请日：2007-08-10

Applicant: Cengiz Palanduz ,  Yongki Min

Inventor： Cengiz Palanduz ,  Yongki Min

IPC: H01G7/00

CPC classification number: H01G4/12 ,  H01L2224/16225 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/017 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/1131 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49155

Abstract: A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material; and sintering the ceramic material. A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material so that the ceramic material is disposed between the first conductive material and the second conductive material; thermal processing at a temperature sufficient to sinter the ceramic material and form a film of the second conductive material; and coating an exposed surface of at least one of the first conduct material and the second conductive material with a different conductive material. An apparatus including first and second electrodes; and a ceramic material between the first electrode and the second electrode, wherein the ceramic material is sintered directly on one of the first and second electrode.

Abstract translation: 一种包括在第一导电材料的片材上直接形成陶瓷材料的方法; 在所述陶瓷材料上形成第二导电材料; 并烧结陶瓷材料。 一种包括在第一导电材料的片材上直接形成陶瓷材料的方法; 在所述陶瓷材料上形成第二导电材料，使得所述陶瓷材料设置在所述第一导电材料和所述第二导电材料之间; 在足以烧结陶瓷材料并形成第二导电材料的膜的温度下进行热处理; 以及用不同的导电材料涂覆第一导电材料和第二导电材料中的至少一个的暴露表面。 一种包括第一和第二电极的装置; 以及在第一电极和第二电极之间的陶瓷材料，其中陶瓷材料直接烧结在第一和第二电极之一上。

公开(公告)号：US20070222030A1

公开(公告)日：2007-09-27

申请号：US11277606

申请日：2006-03-27

Applicant: Islam Salama ,  Yongki Min

Inventor： Islam Salama ,  Yongki Min

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2203/1105

Abstract: Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括形成在集成电路封装的封装衬底上的薄膜电容器。 薄膜电容器中的至少一个包括在第一和第二电极层之间的第一电极层，第二电极层和电介质层。 第一和第二电极层和电介质层中的每一个单独形成并直接形成在封装衬底上。 描述和要求保护其他实施例。

公开(公告)号：US20070132063A1

公开(公告)日：2007-06-14

申请号：US11304649

申请日：2005-12-14

Applicant: Yongki Min ,  John Guzek

Inventor： Yongki Min ,  John Guzek

IPC: H01L29/00

CPC classification number: H05K1/162 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10674

Abstract: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.

Abstract translation: 在一个实施例中，衬底包括嵌入其中的薄膜电容器。 在一个实施例中，多个粘附孔延伸穿过薄膜电容器。 这些粘附孔可以改善电容器与基片的其它部分的粘合性。