公开(公告)号：US20090145652A1

公开(公告)日：2009-06-11

申请号：US12239306

申请日：2008-09-26

Applicant: Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: C23C18/31 ,  C25D5/00 ,  H01B13/00 ,  B05D5/12 ,  C09D5/10

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Abstract translation: 本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔 并且可以实现高可靠性的导体连接而不退火。 本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属 层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀 以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

公开(公告)号：US20090145649A1

公开(公告)日：2009-06-11

申请号：US12323950

申请日：2008-11-26

Applicant: Michio HORIUCHI ,  Yasue Tokutake ,  Shigeaki Suganuma ,  Naoyuki Koizumi ,  Fumimasa Katagiri

Inventor： Michio HORIUCHI ,  Yasue Tokutake ,  Shigeaki Suganuma ,  Naoyuki Koizumi ,  Fumimasa Katagiri

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4046 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/111 ,  H05K3/222 ,  H05K3/4644 ,  H05K2201/0215 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2224/4569 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754

Abstract: A multi-layered wiring substrate, in which a wiring layer and an insulative layer are alternately arranged, having pads to connect to electronic components at one side thereof and wires to connect the corresponding pads to the wiring layer, is composed so that the multi-layered wiring substrate is provided with through holes in which a resin material is filled, at least a part of the pads is formed on the resin material, and at least a part of the wire is contained in the resin material.

Abstract translation: 其中布线层和绝缘层交替布置的多层布线基板具有连接到其一侧的电子部件的焊盘和将相应焊盘连接到布线层的导线， 层叠布线基板设置有填充有树脂材料的通孔，至少一部分垫片形成在树脂材料上，并且至少一部分线材包含在树脂材料中。

公开(公告)号：US07486921B2

公开(公告)日：2009-02-03

申请号：US11017922

申请日：2004-12-22

Applicant: Naoko Yamaguchi ,  Hideo Aoki ,  Chiaki Takubo

Inventor： Naoko Yamaguchi ,  Hideo Aoki ,  Chiaki Takubo

IPC: G03G15/20

CPC classification number: H05K3/207 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  G03G15/6591 ,  H05K3/1266 ,  H05K3/246 ,  H05K3/4664 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0347 ,  H05K2203/0517

Abstract: According to one mode of the present invention, a method of producing an electronic circuit, comprising forming an integrated resin layer having a prescribed thickness by repeating a resin layer forming process a number of times so that resin layers are layered to be integrated with all the resin layers on a substrate, wherein the resin forming process comprises charging the surface of a photoconductor; forming an electrostatic latent image having a prescribed pattern on the surface of the charged photoconductor; forming a visible image by electrostatically attaching charged particles composed of resin on the surface of the photoconductor on which the electrostatic latent image is formed; transferring the visible image formed on the surface of the photoconductor and composed of the charged particles onto the substrate; and fixing said visible image transferred onto said substrate on said substrate to form the resin layer on said substrate, is provided.

Abstract translation: 根据本发明的一个方式，一种电子电路的制造方法，其特征在于，通过重复树脂层形成工序多次来形成具有规定厚度的一体化树脂层，使树脂层层叠成与所有的 树脂层，其中所述树脂形成工艺包括对光电导体的表面进行充电; 在带电的感光体的表面上形成具有规定图案的静电潜像; 通过在其上形成有静电潜像的感光体的表面上静电附着由树脂构成的带电粒子来形成可见图像; 将形成在感光体的表面上的由带电粒子构成的可见图像转印到基板上; 并且将所述转印到所述基板上的所述可见图像固定在所述基板上，以在所述基板上形成树脂层。

公开(公告)号：US20080290142A1

公开(公告)日：2008-11-27

申请号：US11752382

申请日：2007-05-23

Applicant: Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

Inventor： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

IPC: B23K35/24 ,  B23K101/36 ,  B23K31/02

CPC classification number: B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

Abstract translation: 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

公开(公告)号：US20080230152A1

公开(公告)日：2008-09-25

申请号：US12038098

申请日：2008-02-27

Applicant: Martin Standing

Inventor： Martin Standing

IPC: B23K35/24

CPC classification number: H05K3/3484 ,  B23K35/025 ,  B23K35/24 ,  B23K35/362 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/73153 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K2201/0215 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A paste for forming interconnects that includes a quantity of metallic binder particles, a quantity of metallic filler particles, and a quantity of flux.

Abstract translation: 一种用于形成互连件的糊料，其包括一定量的金属粘合剂颗粒，一定量的金属填料颗粒和一定量的助熔剂。

公开(公告)号：US20080160331A1

公开(公告)日：2008-07-03

申请号：US12038404

申请日：2008-02-27

Applicant: Yoichi Kukimoto ,  Kazuki Ikeda ,  Hitoshi Sakurai

Inventor： Yoichi Kukimoto ,  Kazuki Ikeda ,  Hitoshi Sakurai

IPC: B23K35/36 ,  B22F7/00 ,  B22F7/02

CPC classification number: B23K35/025 ,  B22F1/007 ,  B23K35/36 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01327 ,  H05K1/111 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/09381 ,  H05K2203/043 ,  Y10T428/12035 ,  Y10T428/12493 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The present invention relates to a solder paste composition used for precoating an electrode surface with solder. A first solder paste composition is contains a solder powder and a flux, and a metallic powder made by metallic species different from metallic species constituting the solder powder and metallic species constituting the electrode surface in a rate of 0.1% by weight or more and 20% by weight or less based on a total amount of the solder powder. A second solder paste composition contains a deposition solder material which deposits the solder by heating and a flux, and a metallic powder comprising metallic species different from metallic species constituting a metallic component in the deposition solder material and metallic species constituting the electrode surface in a rate of 0.1% by weight or more and 20% by weight or less based on a total amount of the metallic component in the deposition solder material. When these solder paste compositions are evenly applied onto an electronic circuit substrate for precoating, such a solder that does not generate any swollen portion, solder-lacking portion and variability in a height thereof can be formed irrespective of a shape of a pad.

Abstract translation: 本发明涉及一种用于用焊料预涂电极表面的焊膏组合物。 第一焊膏组合物含有焊料粉末和焊剂，以及由构成焊料粉末的金属物质的金属物质构成的金属粉末和构成电极表面的金属物质的比例为0.1重量％以上且20重量％ 或更少的焊锡粉末。 第二焊膏组合物包含通过加热和焊剂沉积焊料的沉积焊料材料和包含金属物质的金属粉末，所述金属粉末包含不同于沉积焊料材料中构成金属成分的金属物质和构成电极表面的金属物质的速率 相对于沉积焊料的金属成分的总量为0.1重量％以上且20重量％以下。 当将这些焊膏组合物均匀地涂覆到用于预涂层的电子电路基板上时，可以形成不产生任何溶胀部分的焊料，焊料缺乏部分和其高度的变化性，而与焊盘的形状无关。

公开(公告)号：US20080102565A1

公开(公告)日：2008-05-01

申请号：US11529011

申请日：2006-09-28

Applicant: Xiang Yin Zeng ,  Daoqiang (Daniel) Lu ,  Jiangqi He ,  Jiamiao (John) Tang

Inventor： Xiang Yin Zeng ,  Daoqiang (Daniel) Lu ,  Jiangqi He ,  Jiamiao (John) Tang

IPC: H01L21/00

CPC classification number: H05K1/0234 ,  H01L23/49827 ,  H01L23/552 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0373 ,  H05K2201/0215 ,  H05K2201/0323 ,  H05K2201/10378 ,  Y10T428/24917 ,  H01L2224/0401

Abstract: In one embodiment, the present invention includes a semiconductor package with lossy material inserts. The lossy material inserts may reduce electronic noise such as package resonance. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有有损材料插入物的半导体封装。 有损耗的材料插入物可以减少诸如封装谐振的电子噪声。 描述和要求保护其他实施例。

公开(公告)号：US20080081209A1

公开(公告)日：2008-04-03

申请号：US11693107

申请日：2007-03-29

Applicant: Woong Sun Lee

Inventor： Woong Sun Lee

IPC: H01L29/12 ,  H01L21/3205

CPC classification number: H05K3/185 ,  H01L23/13 ,  H01L23/145 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/15157 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/183 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/182 ,  H05K2201/0215 ,  H05K2201/09845 ,  H05K2203/107 ,  Y10T428/12528 ,  H01L2924/00

Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Abstract translation: 用于实施多封装的基板包括下层，其具有包含导电填料的聚合物材料，并且设置有分为台阶部分和底部的阶梯状凹槽; 形成在下层之上的涂层，形成涂层，使得其可以在台阶部分上形成金属线形成区域，并且在金属线形成区域中的阶梯状沟槽和导电填料的底部 被暴露 以及金属线，其通过使用在由涂层限定的金属线形成区域中的暴露的导电填料作为种子层的电镀工艺形成。

公开(公告)号：US20070232059A1

公开(公告)日：2007-10-04

申请号：US11474453

申请日：2006-06-26

Applicant: Tomoyuki Abe

Inventor： Tomoyuki Abe

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H05K3/4614 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/3473 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/462 ,  H05K2201/0215 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A multilayer interconnection substrate is disclosed that includes a multilayer interconnection layer having at least a first interconnection layer and a second interconnection layer stacked with an insulating layer provided therebetween, and a connection via configured to electrically connect the first interconnection layer and the second interconnection layer. The connection via includes an internal conductor and a metal film covering the internal conductor. The internal conductor is an aggregate of metal particles.

Abstract translation: 公开了一种多层互连衬底，其包括具有至少第一互连层和层叠有设置在其间的绝缘层的第二互连层的多层互连层，以及经配置以电连接第一互连层和第二互连层的连接通孔。 连接通孔包括内部导体和覆盖内部导体的金属膜。 内部导体是金属颗粒的聚集体。

公开(公告)号：US20070224737A1

公开(公告)日：2007-09-27

申请号：US11385271

申请日：2006-03-21

Applicant: Carl Berlin ,  Deepukumar Nair ,  Matthew Walsh

Inventor： Carl Berlin ,  Deepukumar Nair ,  Matthew Walsh

IPC: H01L21/20

CPC classification number: H01P1/203 ,  H01P1/2005 ,  H05K1/0233 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/0215 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2203/0557 ,  H05K2203/104 ,  H05K2203/171

Abstract: Tuned Electromagnetic Bandgap (EBG) devices, and a method for making and tuning tuned EBG devices are provided. The method includes the steps of providing first and second overlapping substrates, placing magnetically alignable conductive material between the substrates, and applying a magnetic field in the vicinity of the magnetically alignable conductive material to align at least some of the material into conductive vias. The method further includes the steps of physically altering via characteristics of EBG devices to tune the bandpass and resonant frequencies of the EBG devices.

Abstract translation: 提供了调谐电磁带隙（EBG）器件，以及用于制造和调谐调谐EBG器件的方法。 该方法包括以下步骤：提供第一和第二重叠基板，将磁性取向的导电材料放置在基板之间，以及在可磁对准导电材料附近施加磁场，使至少一些材料对准导电通孔。 该方法还包括通过EBG器件的特性物理地改变以调节EBG器件的带通和谐振频率的步骤。