公开(公告)号：US20050126682A1

公开(公告)日：2005-06-16

申请号：US11050519

申请日：2005-02-03

Applicant: Mitsuyoshi Nishide ,  Ryoji Nakamura ,  Norio Sakai

Inventor： Mitsuyoshi Nishide ,  Ryoji Nakamura ,  Norio Sakai

IPC: B28B11/00 ,  H01L21/48 ,  H05K1/09 ,  H05K3/46 ,  C03B29/00 ,  H05K1/02 ,  H05K1/03

CPC classification number: B32B18/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/208 ,  B32B2307/538 ,  B32B2311/04 ,  B32B2311/08 ,  B32B2311/12 ,  C04B2235/3215 ,  C04B2235/3217 ,  C04B2235/36 ,  C04B2235/658 ,  C04B2237/40 ,  C04B2237/407 ,  C04B2237/408 ,  C04B2237/56 ,  C04B2237/562 ,  C04B2237/565 ,  C04B2237/706 ,  H01L21/481 ,  H01L21/4857 ,  H05K1/09 ,  H05K1/092 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/0317 ,  H05K2201/0352 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T428/24926

Abstract: A monolithic ceramic substrate includes a green laminate having a plurality of green functional ceramic layers including a functional ceramic material, green support layers including a ceramic material that does not sinter at a sintering temperature for the green functional ceramic material to prevent shrinkage of the functional ceramic layers, first conductor patterns including a thin-film conductor, and second conductor patterns including a thick-film conductor. The green laminate is fired at the sintering temperature for the green functional ceramic material.

公开(公告)号：US20050117257A1

公开(公告)日：2005-06-02

申请号：US10864073

申请日：2004-06-08

Applicant: Visit Thaveeprungsriporn ,  Szu-Han Hu

Inventor： Visit Thaveeprungsriporn ,  Szu-Han Hu

IPC: G11B5/48 ,  G11B33/14 ,  H02B1/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/05 ,  H05K3/28

CPC classification number: G11B5/486 ,  G11B5/40 ,  G11B5/484 ,  G11B33/1493 ,  H05K1/0259 ,  H05K1/0393 ,  H05K1/056 ,  H05K3/28 ,  H05K2201/0317 ,  H05K2201/0323

Abstract: Techniques for preventing electrostatic discharge (ESD) and circuit noise are provided. More particularly, the present invention provides a method to prevent ESD damage during the assembly of computer disk commonly called a hard disk for memory applications. The coating mainly involves a ion-deposition process. Merely by way of example, the present invention is implemented by using filtered cathodic vacuum arc (FCVA) with a dissipative crystalline and/or amorphous carbon base thin film coating on a flexible circuit to drain the potential electrostatic charges during circuit assembly and interconnect processes, yet it would be recognized that the invention has a much broader range of applicability on any electronic apparatus that is susceptible to electrostatic damage and static noise.

Abstract translation: 提供了防止静电放电（ESD）和电路噪声的技术。 更具体地，本发明提供了一种在计算机盘的组装期间防止ESD损坏的方法，通常称为用于存储器应用的硬盘。 涂层主要涉及离子沉积工艺。 仅作为示例，本发明通过在柔性电路上使用具有耗散结晶和/或无定形碳基薄膜涂层的过滤阴极真空电弧（FCVA）来实现，以在电路组装和互连过程期间排出潜在的静电电荷， 但是应当认识到，本发明在易受静电损伤和静态噪声的任何电子设备上具有更广泛的应用范围。

公开(公告)号：US06786737B2

公开(公告)日：2004-09-07

申请号：US10167415

申请日：2002-06-13

Applicant: Tomishige Tai ,  Mitsuo Koguchi

Inventor： Tomishige Tai ,  Mitsuo Koguchi

IPC: H01R909

CPC classification number: H05K3/20 ,  H01R12/52 ,  H05K3/4038 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2203/0108 ,  H05K2203/0338 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49176 ,  Y10T29/4921 ,  Y10T29/4922 ,  Y10T29/49222

Abstract: A metallic thin film 15 is formed on a mold 11 having protrusions 12 complementary in shape to a conductor pattern to be formed; a substrate 17 having a transfer layer 16 of adherent (or adhesive) material applied to one side surface thereof is provided; and the transfer layer 16 side of the substrate is brought into intimate contact with the metallic thin film 15 laid over the protrusions 12, followed by pulling the transfer layer apart from the mold so as to transfer the metallic thin film 15 covering the protrusions 12 onto the transfer layer 16 to thereby form the conductor pattern 18 on the transfer layer 16. The metal film may include cooper and a weak adherence layer 13 which may be gold.

Abstract translation: 在具有与要形成的导体图案形状互补的突起12的模具11上形成金属薄膜15; 提供具有施加到其一个侧表面的粘附（或粘合）材料的转印层16的基板17; 使基板的转印层16侧与布置在突起12上的金属薄膜15紧密接触，然后将转印层拉离模具，将覆盖突起12的金属薄膜15转印到 转印层16，从而在转印层16上形成导体图案18.金属膜可以包括铜和弱粘附层13，其可以是金。

公开(公告)号：US06771160B2

公开(公告)日：2004-08-03

申请号：US09921074

申请日：2001-08-02

Applicant: Jiangtao Wang ,  Michael A. Centanni ,  Sidney J. Clouser

Inventor： Jiangtao Wang ,  Michael A. Centanni ,  Sidney J. Clouser

IPC: H01C1012

CPC classification number: H05K1/167 ,  H01C7/18 ,  H01C17/07 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  H05K2203/0723 ,  Y10S29/016 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49101 ,  Y10T29/49156

Abstract: A resistor foil, comprised of a copper layer having a first side and a second side. An intermediate layer having a thickness of between 5 Å and 70 Å is disposed on the first side of the copper layer. A first layer of a first resistor metal having a thickness of between 50 Å and 2 &mgr;m is disposed on the intermediate layer, and a second layer of a second resistor metal having a thickness of between 50 Å and 2 &mgr;m is disposed on the first layer of the first resistor metal. The first resistor metal has a resistance different from the second resistor metal.

Abstract translation: 一种电阻箔，由具有第一面和第二面的铜层构成。 在铜层的第一侧上设置厚度介于5埃和70埃之间的中间层。 在中间层上设置厚度为50埃至2微米的第一电阻金属的第一层，并且具有50埃至2微米厚度的第二电阻金属的第二层设置在第一层 的第一个电阻金属。 第一电阻金属具有与第二电阻金属不同的电阻。

公开(公告)号：US20040131779A1

公开(公告)日：2004-07-08

申请号：US10666912

申请日：2003-09-19

Applicant: SiPix Imaging, Inc.

Inventor： Jeanne E. Haubrich ,  Yi-Shung Chaug ,  Zarng-Arh George Wu ,  Rong-Chang Liang

IPC: B05D005/12 ,  B05D005/00

CPC classification number: G02F1/13439 ,  H05K3/04 ,  H05K3/048 ,  H05K3/146 ,  H05K3/16 ,  H05K3/184 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2203/0257 ,  H05K2203/0264 ,  H05K2203/0522 ,  H05K2203/0746 ,  Y10S156/922 ,  Y10T156/11

Abstract: A process for forming a patterned thin film structure on a substrate is disclosed. A pattern is printed with a material, such as a masking coating or an ink, on the substrate, the pattern being such that, in one embodiment, the desired thin film structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structures.

Abstract translation: 公开了一种在衬底上形成图案化薄膜结构的工艺。 在衬底上印有诸如掩模涂层或油墨的材料的图案，该图案使得在一个实施例中，将在不存在印刷材料的区域中形成所需的薄膜结构， 即，印刷要形成的薄膜结构的负像。 在另一个实施例中，图案印刷有难以从衬底剥离的材料，并且所需的薄膜结构将形成在存在印刷材料的区域中，即，薄膜结构的正像是 印刷。 薄膜材料沉积在图案化的衬底上，并且不期望的区域被剥离，留下图案化的薄膜结构。

公开(公告)号：US20040109298A1

公开(公告)日：2004-06-10

申请号：US10644386

申请日：2003-08-19

Inventor： William F. Hartman ,  Kirk M. Slenes ,  Kristen J. Law

IPC: C04B035/468

CPC classification number: H05K1/162 ,  B32B27/00 ,  H05K3/4611 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0317 ,  H05K2201/09309

Abstract: A dielectric substrate useful in the manufacture of printed wiring boards is disclosed wherein the dielectric substrate comprises at least one organic polymer having a Tg greater than 140null C. and at least one filler material. The dielectric substrate of this invention has a dielectric constant that varies less than 15% over a temperature range of from null55 to 125null C. Additionally, a method for producing integral capacitance components for inclusion within printed circuit boards. Hydrothermally prepared nanopowders permit the fabrication of very thin dielectric layers that offer increased dielectric constants and are readily penetrated by microvias. Disclosed is a method of preparing a slurry or suspension of a hydrothermally prepared nanopowder and solvent. A suitable bonding material, such as a polymer is mixed with the nanopowder slurry, to generate a composite mixture that is formed into a dielectric layer. The dielectric layer may be placed upon a conductive layer prior to curing, or conductive layers may be applied upon a cured dielectric layer, either by lamination or by metallization processes, such as vapor deposition or sputtering.

Abstract translation: 公开了一种用于制造印刷线路板的电介质基片，其中电介质基片包括Tg大于140℃的至少一种有机聚合物和至少一种填料。 本发明的电介质基板的介电常数在-55〜125℃的温度范围内变化小于15％。另外，制造用于包含在印刷电路板内的积分电容元件的方法。 水热制备的纳米粉末允许制造非常薄的介电层，其提供增加的介电常数并且容易被微孔穿透。 公开了制备水热制备的纳米粉末和溶剂的浆料或悬浮液的方法。 将合适的粘合材料，例如聚合物与纳米粉末浆料混合，以产生形成介电层的复合混合物。 介电层可以在固化之前放置在导电层上，或者可以通过层压或通过金属化工艺，例如气相沉积或溅射将导电层施加在固化的介电层上。

公开(公告)号：US20030227592A1

公开(公告)日：2003-12-11

申请号：US10454580

申请日：2003-06-05

Inventor： Yoshihiro Izumi ,  Toshihiko Nakagawa

IPC: G02F001/1345

CPC classification number: H05K1/0265 ,  G02F1/1345 ,  H01L2924/0002 ,  H05K3/20 ,  H05K3/24 ,  H05K3/323 ,  H05K2201/0317 ,  H05K2201/09736 ,  H01L2924/00

Abstract: A wiring substrate is arranged so that a first periphery electric wiring and a second periphery electric wiring are patterned on an active matrix substrate, and a TCP as a electronic component is provided on a portion of the patterned electric wiring. The first periphery electric wiring and the second periphery electric wiring are formed by including a metal thin film and a transferred metal film. Further, in the portion where the TCP is provided, the first periphery electric wiring and the second periphery electric wiring either have a monolayer structure with one of the metal thin film and the transferred metal film, or have a lamination structure with both of the metal thin film and the transferred metal film. On this account, connection failure can be prevented on a low resistance wiring substrate.

Abstract translation: 布线基板被布置成使得第一周边电布线和第二周边电布线在有源矩阵基板上图案化，并且在图案化电布线的一部分上设置作为电子部件的TCP。 第一周边电布线和第二周边电布线通过包括金属薄膜和转移的金属膜而形成。 此外，在设置有TCP的部分中，第一周边电布线和第二周边电布线也具有与金属薄膜和转印金属膜之一的单层结构，或者具有与金属的两者的层叠结构 薄膜和转移的金属膜。 因此，可以防止在低电阻布线基板上的连接故障。

公开(公告)号：US20030218233A1

公开(公告)日：2003-11-27

申请号：US10440922

申请日：2003-05-19

Applicant: Alps Electric Co., Ltd.

Inventor： Kazuhiko Ueda ,  Seiichi Yokoyama

IPC: H01L029/00

CPC classification number: H01L23/49805 ,  H01L24/48 ,  H01L25/165 ,  H01L27/0641 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/16 ,  H05K3/244 ,  H05K3/403 ,  H05K2201/0317 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Thin film circuit elements including capacitors, resistors, and inductance elements are formed on a large substrate, and semiconductor chips are wire bonded to the substrate. The elements and chips are sealed by potting a sealing resin. The large substrate is divided into multiple stripe substrates by dicing and a thin-film conductive layer is sputtered on cut surfaces of the stripe substrates, thereby electrically connecting edges of lower conductive patterns to edges of upper conductive patterns exposed from side surfaces of the sealing resin through the thin-film conductive layer. A Ni foundation layer and Au layer are successively plated on a surface of the thin-film conductive layer to form edge electrodes on side surfaces of the stripe substrates and the stripe substrates are divided finely into individual alumina substrates.

Abstract translation: 包括电容器，电阻器和电感元件的薄膜电路元件形成在大的衬底上，并且半导体芯片被引线接合到衬底。 元件和芯片通过灌封密封树脂来密封。 通过切割将大衬底分成多个条形衬底，并且在条形衬底的切割表面上溅射薄膜导电层，从而将下导电图案的边缘电连接到从密封树脂的侧表面露出的上导电图案的边缘 通过薄膜导电层。 Ni基底层和Au层依次电镀在薄膜导电层的表面上，以在条形基板的侧表面上形成边缘电极，并将条形基片细分成单独的氧化铝基片。

公开(公告)号：US06552384B2

公开(公告)日：2003-04-22

申请号：US09898670

申请日：2001-07-02

Applicant: Shinji Murata ,  Ken Yamamura ,  Mitsuru Tokuta

Inventor： Shinji Murata ,  Ken Yamamura ,  Mitsuru Tokuta

IPC: H01L2362

CPC classification number: H01L28/40 ,  H01L2224/4813 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/09909

Abstract: In order to provide an electronic circuit board capable of preventing the breakdown voltage of a capacitor element from dropping and excellent in high frequency performance, a positive type photoresist is spin-coated over the surface of an alumina substrate and is exposed to light and developed to form an insulating layer partially, followed by formation of a capacitor element by successively stacking a lower electrode, a dielectric layer and an upper electrode over this insulating layer, further followed by formation of a resistance element, an inductor element and a transmission line, each in a filmy state, over the surface of the alumina substrate.

公开(公告)号：US20030039811A1

公开(公告)日：2003-02-27

申请号：US10203970

申请日：2002-09-18

Inventor： Toshio Sugawa ,  Satoshi Murakawa ,  Masaaki Hayama ,  Takeo Yasuho

IPC: B32B007/00

CPC classification number: H05K3/4069 ,  H05K1/095 ,  H05K2201/0305 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/1461 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board is manufactured by filling a via-hole formed in an insulating substrate with conductive material, disposing conductive layers on both sides of the insulating substrate, and forming alloy of component material of the conductive material with component material of the conductive layers. In the circuit board, therefore, the conductive material filled in the via-hole formed in the insulating substrate is securely connected electrically as well as mechanically to the conductive layers on both sides of the insulating substrate with high reliability.

Abstract translation: 通过用导电材料填充形成在绝缘基板中的通孔来制造电路板，在绝缘基板的两侧设置导电层，以及将导电材料的组分材料的合金与导电层的成分材料形成。 因此，在电路板中，填充在形成于绝缘基板上的通路孔中的导电材料与绝缘基板两侧的导电层电连接并且机械地牢固地连接在一起，具有高可靠性。