公开(公告)号：US20110061912A1

公开(公告)日：2011-03-17

申请号：US12654668

申请日：2009-12-29

Applicant: Myung Sam Kang ,  Mi Sun Hwang ,  Ok Tae Kim ,  Seon Ha Kang ,  Gil Yong Shin ,  Kil Yong Yun ,  Min Jung Cho

Inventor： Myung Sam Kang ,  Mi Sun Hwang ,  Ok Tae Kim ,  Seon Ha Kang ,  Gil Yong Shin ,  Kil Yong Yun ,  Min Jung Cho

IPC: H05K1/00 ,  H05K1/11 ,  B32B38/10 ,  B29C65/00

CPC classification number: H05K3/4611 ,  H05K3/045 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2203/1461 ,  H05K2203/1536 ,  Y10T156/10

Abstract: Provided are a printed circuit board (PCB), and a manufacturing method thereof. The PCB includes a stacked structure including second and third insulation layers with a first insulation layer interposed therebetween, and a conductive via having first to fourth conductive vias. A second-layer circuit pattern and a third-layer circuit pattern are buried in the first insulation layer, a first-layer circuit pattern is formed on the second insulation layer, and a fourth-layer circuit pattern is formed on the third insulation layer. A first conductive via connects the first-layer circuit pattern and the second-layer circuit pattern, a second conductive via connects the first-layer circuit pattern and the third-layer circuit pattern, a third conductive via connects the second-layer circuit pattern and the fourth-layer circuit pattern, and a fourth conductive via connects the third-layer circuit pattern and the fourth-layer circuit pattern.

Abstract translation: 提供了一种印刷电路板（PCB）及其制造方法。 PCB包括堆叠结构，其包括其间插入有第一绝缘层的第二绝缘层和第三绝缘层，以及具有第一至第四导电通孔的导电通孔。 在第一绝缘层中埋设第二层电路图形和第三层电路图案，在第二绝缘层上形成第一层电路图案，在第三绝缘层上形成第四层电路图形。 第一导电通孔连接第一层电路图案和第二层电路图案，第二导电通孔连接第一层电路图案和第三层电路图案，第三导电通孔连接第二层电路图案和 第四层电路图案和第四导电通孔连接第三层电路图案和第四层电路图案。

公开(公告)号：US20110058340A1

公开(公告)日：2011-03-10

申请号：US12941899

申请日：2010-11-08

Applicant: Yonggang Li ,  Islam Salama ,  Charan Gurumurthy

Inventor： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy

IPC: H05K7/00

CPC classification number: H05K3/422 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  Y10T29/49128 ,  Y10T29/49165

Abstract: A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.

Abstract translation: 一种制造衬底芯结构的方法，以及根据该方法形成的衬底芯结构。 该方法包括：通过起始绝缘层激光钻探第一组通路孔; 用导电材料填充第一组通孔开口以提供第一组导电通孔; 在起始绝缘层的相对侧上提供第一和第二图案化导电层; 在所述第一图案化导电层上提供补充绝缘层; 激光钻穿通过补充绝缘层的第二组通孔; 用导电材料填充第二组通孔开口以提供第二组导电通路; 以及在所述补充绝缘层的暴露侧上提供补充图案化导电层，所述第二组导电通孔在其相对侧与所述第一图案化导电层和所述补充图案化导电层接触。

公开(公告)号：US07892441B2

公开(公告)日：2011-02-22

申请号：US11806598

申请日：2007-06-01

Applicant: Deepak K. Pai

Inventor： Deepak K. Pai

IPC: H01B13/00 ,  H01K3/10

CPC classification number: H05K3/4007 ,  H01L21/486 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/113 ,  H05K2201/0394 ,  H05K2201/09881 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A method of manufacturing an interposer is provided, including the steps of providing a sheet with a copper layer and polyimide layer, laser drilling holes in the polyimide layer down to the copper layer, filling the holes with copper and extending the copper above the polyimide layer to define caps, removing portions of the copper layer to form conductive pads, and filling gaps between the conductive pads with an insulator, wherein individual conductive pads are in electrical contact with corresponding individual caps.

Abstract translation: 提供一种制造插入件的方法，包括以下步骤：提供具有铜层和聚酰亚胺层的片材，在聚酰亚胺层中的铜层下方的激光钻孔，用铜填充孔并将铜延伸到聚酰亚胺层上方 以限定帽，去除铜层的部分以形成导电焊盘，以及用绝缘体填充导电焊盘之间的间隙，其中各个导电焊盘与相应的单独盖电接触。

公开(公告)号：US20110036486A1

公开(公告)日：2011-02-17

申请号：US12926011

申请日：2010-10-20

Applicant: Myung-Sam Kang

Inventor： Myung-Sam Kang

IPC: B32B38/00

CPC classification number: H05K3/0035 ,  B32B15/14 ,  B32B15/20 ,  B32B2038/0076 ,  B32B2250/40 ,  B32B2255/06 ,  B32B2255/205 ,  B32B2260/021 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2305/076 ,  B32B2311/00 ,  B32B2457/00 ,  B32B2535/00 ,  C25D5/12 ,  C25D5/48 ,  H05K3/0038 ,  H05K3/025 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2203/0361 ,  H05K2203/1388 ,  Y10T29/49165 ,  Y10T428/1275 ,  Y10T428/12778

Abstract: A method of manufacturing a metal clad laminate, the method including: forming a barrier layer over one side of a metal layer by performing plating; forming a metal foil over one side of the barrier layer by performing plating; and attaching an insulator to one side of the metal foil. In a further embodiment, the method of manufacturing a metal clad laminate, the method including: attaching a metal foil to one or either side of an insulator; and forming a barrier layer over the metal foil by way of electroplating.

Abstract translation: 一种制造覆金属层压板的方法，所述方法包括：通过进行电镀在金属层的一侧上形成阻挡层; 通过进行电镀在阻挡层的一侧上形成金属箔; 以及将绝缘体连接到所述金属箔的一侧。 在另一实施例中，制造覆金属箔层压板的方法，该方法包括：将金属箔连接到绝缘体的一侧或两侧; 并通过电镀在金属箔上形成阻挡层。

公开(公告)号：US07889510B2

公开(公告)日：2011-02-15

申请号：US11797206

申请日：2007-05-01

Applicant: Satoshi Takeuchi ,  Hiroki Kamiya ,  Katsunori Kubota ,  Motoki Shimizu

Inventor： Satoshi Takeuchi ,  Hiroki Kamiya ,  Katsunori Kubota ,  Motoki Shimizu

IPC: H05K1/18

CPC classification number: G01R31/2818 ,  G01R31/2812 ,  H05K1/0268 ,  H05K1/186 ,  H05K3/4614 ,  H05K3/4617 ,  H05K2201/0394 ,  H05K2201/09254 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

Abstract: A component-embedded board device has a wiring board in which an electronic component is embedded, a connection member which is conductive and arranged at a surface of the wiring board, and an inner wiring unit which is arranged in the wiring board and connects an electrode of the electronic component with the connection member. The component-embedded board device is further provided with an inspection connection member for an inspection of a faulty wiring of the inner wiring unit, and an inspection wiring unit which is arranged in the wiring board and connects the inspection connection member with one of the electrode and a predetermined portion of the inner wiring unit. The inspection connection member is conductive and arranged at a surface of the wiring board.

Abstract translation: 组件嵌入式板装置具有嵌入有电子部件的布线基板，导电性配置在配线基板的表面的连接部件和配置在配线基板上的内部配线部， 的电子部件。 组件嵌入式板装置还具有用于检查内部布线单元的故障布线的检查连接构件和布置在布线板中并将检查连接构件与电极之一连接的检查布线单元 和内部布线单元的预定部分。 检查连接构件是导电的并且布置在布线板的表面上。

公开(公告)号：US20110024164A1

公开(公告)日：2011-02-03

申请号：US12887197

申请日：2010-09-21

Applicant: Motoo ASAI ,  Dongdong WANG ,  Takahiro MORI

Inventor： Motoo ASAI ,  Dongdong WANG ,  Takahiro MORI

IPC: H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core structure comprising resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, and the first via hole and the second via hole include a metal filling up to the respective top of openings formed in the resin layers, respectively, sandwich one or more conductor circuits in the core structure and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers.

Abstract translation: 一种多层印刷电路板，包括由树脂层和由树脂层夹持的导体电路的芯结构，芯结构具有在第一表面的相对侧上的第一表面和第二表面，第一导体层包括导体电路 形成在芯结构的第一表面上，以及第二导体层，包括形成在芯结构的第二表面上的导体电路。 芯结构包括第一通孔和第二通孔，并且第一通孔和第二通孔分别包括填充到树脂层中形成的开口的相应顶部的金属，将一个或多个导体电路夹在 芯结构并且垂直定位以形成电连接第一和第二导体层的各个导体电路的通孔。

公开(公告)号：US07856706B2

公开(公告)日：2010-12-28

申请号：US12381925

申请日：2009-03-17

Applicant: Raj Kumar ,  Monte Dreyer ,  Michael J. Taylor

Inventor： Raj Kumar ,  Monte Dreyer ,  Michael J. Taylor

IPC: H05K3/36

CPC classification number: H05K3/4623 ,  H05K3/205 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0271 ,  H05K2203/0502 ,  H05K2203/061 ,  H05K2203/0733 ,  H05K2203/107 ,  H05K2203/1461 ,  H05K2203/1536 ,  H05K2203/304 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.

Abstract translation: 一种制造印刷电路板的至少一部分的方法。 该方法包括：在第一多层基板上施加层压粘合剂，该第一多层基板包括多个电路层，在第一多层基板的第一侧具有至少一个第一金属焊盘; 在层压粘合剂上涂上保护膜; 将至少一个通孔形成到所述层压粘合剂中以暴露所述第一多层基板的第一侧上的所述至少一个金属焊盘; 将至少一个导电浆料填充到在层压粘合剂中形成的至少一个通孔中; 去除所述保护膜以将所述层叠粘合剂暴露在所述第一多层基板上; 以及在所述第二多层基板的第二面上，将具有包含多个电路层的第二多层基板与至少一个第二金属焊盘连接的第一多层基板。

公开(公告)号：US20100304298A1

公开(公告)日：2010-12-02

申请号：US12788837

申请日：2010-05-27

Applicant: Katsutoshi Hirashima ,  Hirofumi Fujii ,  Yasushi Tamura ,  Ryouji Suezaki

Inventor： Katsutoshi Hirashima ,  Hirofumi Fujii ,  Yasushi Tamura ,  Ryouji Suezaki

IPC: G03F7/20 ,  G03F7/004

CPC classification number: G03F7/0387 ,  G03F7/0045 ,  G03F7/38 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/287 ,  H05K3/4092 ,  H05K2201/0154 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/0969 ,  H05K2203/056 ,  H05K2203/1476 ,  Y10S430/107

Abstract: A negative photosensitive material is provided which has a lower linear expansion coefficient and a lower hygroscopic expansion coefficient and is excellent in gradational patternability and PI etchability in patterning. The negative photosensitive material comprises:(A) a polyimide precursor having a structural unit represented by the following general formula (1) and a structural unit represented by the following general formula (2), the structural unit represented by the general formula (2) being present in the polyimide precursor in a proportion of less than 30 mol % based on the overall amount of the polyimide precursor; and (B) at least one of a pyridine derivative represented by the following general formula (3) and a pyridine derivative represented by the following general formula (4): wherein R1, R2, R3, R4 and R5, which may be the same or different, are each a C1 to C4 alkyl group, and Ar is an aryl group having a nitro group at its ortho position, wherein R1, R2, R4 and R5, which may be the same or different, are each a C1 to C4 alkyl group, and Ar is an aryl group having a nitro group at its ortho position.

Abstract translation: 提供具有较低线性膨胀系数和较低吸湿膨胀系数的负型感光材料，并且在图案化中具有优异的梯度图案性和PI可蚀刻性。 负型感光材料包括：（A）具有由以下通式（1）表示的结构单元和由以下通式（2）表示的结构单元的聚酰亚胺前体，由通式（2）表示的结构单元， 以聚酰亚胺前体的总量小于30mol％的比例存在于聚酰亚胺前体中; 和（B）由以下通式（3）表示的吡啶衍生物和由以下通式（4）表示的吡啶衍生物中的至少一种：其中R1，R2，R3，R4和R5可以相同 或不同的，各自为C1〜C4烷基，Ar为其邻位具有硝基的芳基，其中R1，R2，R4和R5可以相同或不同，分别为C1〜C4 烷基，Ar是在其邻位具有硝基的芳基。

公开(公告)号：US07825340B2

公开(公告)日：2010-11-02

申请号：US12193492

申请日：2008-08-18

Applicant: Hitoshi Kashio

Inventor： Hitoshi Kashio

IPC: H05K1/11

CPC classification number: H05K1/0271 ,  H05K1/112 ,  H05K3/0017 ,  H05K3/064 ,  H05K2201/0394 ,  H05K2201/09063 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/0554

Abstract: In one embodiment of the present invention, a connecting device of a double-sided wiring board includes a first-side connecting land portion configured by a first-side conductive layer and a first-side connecting conductive layer and a second-side connecting land portion configured by a second-side conductive layer; the first-side connecting land portion and the second-side connecting land portion face each other at respective central portions with an insulating substrate sandwiched therebetween; a substrate hole is formed corresponding to a peripheral end portion of the first-side connecting land portion and a peripheral end portion of the second-side connecting land portion; and the peripheral end portion of the first-side connecting land portion and the peripheral end portion of the second-side connecting land portion are connected to each other via the substrate hole.

Abstract translation: 在本发明的一个实施例中，双面布线板的连接装置包括由第一侧导电层和第一侧连接导电层构成的第一侧连接接地部分和第二侧连接接地部分 由第二侧导电层构成; 所述第一侧连接接地部和所述第二侧连接用接地部在各自的中央部彼此面对，并且将绝缘基板夹在其间; 与第一侧连接接地部的周缘部和第二侧连接接地部的周缘部对应地形成基板孔; 并且第一侧连接接地部分的周边端部和第二侧连接接地部分的周边端部经由基板孔相互连接。

公开(公告)号：US20100252318A1

公开(公告)日：2010-10-07

申请号：US12819805

申请日：2010-06-21

Applicant: Michimasa TAKAHASHI ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

Inventor： Michimasa TAKAHASHI ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

IPC: H05K1/02

CPC classification number: H01L23/48 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/00 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09827 ,  Y10T29/49124 ,  H01L2924/00

Abstract: A multilayer printed wiring board including insulating layers, conductor layers stacked alternately over the insulating layers, respectively, and viaholes formed in the insulation layers and electrically connecting the conductor layers through the insulation layers. The viaholes include a first group of viaholes and a second group of viaholes. The viaholes in the first group are tapered toward the viaholes in the second group, and the viaholes in the second group are tapered toward the viaholes in the first group. The viaholes in the first group and the the viaholes in the second group are formed in the insulating layers, respectively, and the viaholes are formed by plating openings formed after lamination of respective ones of the insulating layers, and each of the insulating layers is about 100 μm or less in thickness.

Abstract translation: 一种多层印刷布线板，分别包括绝缘层，交替地层叠在绝缘层上的导体层和形成在绝缘层中的通孔，并通过绝缘层电连接导体层。 通孔包括第一组通孔和第二组通孔。 第一组中的通孔朝向第二组中的通孔逐渐变细，第二组中的通孔在第一组中朝向通孔逐渐变细。 第一组中的通孔和第二组中的通孔分别形成在绝缘层中，并且通孔由叠层各绝缘层之后形成的电镀开口形成，并且每个绝缘层为约 厚度为100μm以下。