公开(公告)号：US09960122B2

公开(公告)日：2018-05-01

申请号：US15464393

申请日：2017-03-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/66 ,  H03H7/38 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5389 ,  G06K19/077 ,  H01L23/14 ,  H01L23/145 ,  H01L23/29 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/66 ,  H01L24/17 ,  H01L25/0652 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2924/0002 ,  H01L2924/1421 ,  H01L2924/181 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01Q1/2225 ,  H01Q1/38 ,  H01Q1/405 ,  H01Q7/00 ,  H03H7/38 ,  H04B1/59 ,  H05K1/181 ,  H05K1/185 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/09527 ,  H05K2201/10098 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A composite device includes a substrate and a mounted component mounted on a surface of, or inside, the substrate. The substrate includes a first thermoplastic resin layer. A surface of the mounted component includes a second thermoplastic resin layer that includes a same or a similar material as that of the first thermoplastic resin layer. A bonding layer that bonds the second thermoplastic resin layer and the first thermoplastic resin layer together is provided between the second thermoplastic resin layer and the first thermoplastic resin layer.

公开(公告)号：US09888581B2

公开(公告)日：2018-02-06

申请号：US14794956

申请日：2015-07-09

Applicant: IBIDEN CO., LTD.

Inventor： Yoshinori Takenaka

IPC: H05K3/00 ,  H05K3/30 ,  H05K3/42 ,  H05K1/16 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/30 ,  H05K1/0233 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09672 ,  Y10T29/49021 ,  Y10T29/4913

Abstract: A method for manufacturing a wiring board includes preparing a core structure, forming on a first surface of the core structure a first buildup structure including insulation layers, and forming on a second surface of the core structure on the opposite side of the first surface of the core structure a second buildup structure including insulation layers and an inductor device. The insulation layers in the second buildup structure have thicknesses which are thinner than thicknesses of the insulation layers in the first buildup structure, and the forming of the second buildup structure includes forming the inductor device in the second buildup structure on the second surface of the core structure such that at least a portion of a conductive pattern formed in the core structure is included as a portion of the inductor device.

公开(公告)号：US20180019237A1

公开(公告)日：2018-01-18

申请号：US15714712

申请日：2017-09-25

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L21/683 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US09847325B2

公开(公告)日：2017-12-19

申请号：US15354484

申请日：2016-11-17

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/4763 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US09774070B2

公开(公告)日：2017-09-26

申请号：US14537059

申请日：2014-11-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Nobuo Ikemoto ,  Yuki Wakabayashi ,  Shigeru Tago

IPC: H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/36 ,  H01R12/62 ,  H05K3/00 ,  H05K3/46 ,  H01R103/00 ,  H01R24/50

CPC classification number: H01P3/082 ,  H01P3/08 ,  H01P11/003 ,  H01R12/62 ,  H01R24/50 ,  H01R2103/00 ,  H05K1/0219 ,  H05K1/0225 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0253 ,  H05K1/115 ,  H05K1/118 ,  H05K1/147 ,  H05K3/0052 ,  H05K3/363 ,  H05K3/4623 ,  H05K3/4632 ,  H05K2201/07 ,  H05K2201/09154 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2201/10037 ,  H05K2201/10204 ,  Y10T29/49016

Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

公开(公告)号：US09549468B1

公开(公告)日：2017-01-17

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/16 ,  H05K7/00 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36 ,  H05K3/00 ,  H05K3/22 ,  H05K3/40

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。

公开(公告)号：US09204552B2

公开(公告)日：2015-12-01

申请号：US13685777

申请日：2012-11-27

Applicant: IBIDEN Co., Ltd.

Inventor： Toshiki Furutani ,  Yukinobu Mikado ,  Mitsuhiro Tomikawa

IPC: H05K1/16 ,  H05K1/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/181 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/09527 ,  H05K2201/096

Abstract: A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup structure formed on surface of the substrate and including an interlayer insulation layer, and a second buildup structure formed on the opposing surface of the substrate and including an interlayer insulation layer. The substrate includes a core material portion including multiple resin layers, a first conductive layer formed on first surface of the core portion and a second conductive layer formed on second surface of the core portion, the core portion has opening through the resin layers and accommodating the component, the insulation layer of the first structure is positioned such that the opening of the core portion is covered on the first surface, and the insulation layer of the second structure is positioned such that the opening of the core portion is covered on the second surface.

Abstract translation: 印刷电路板包括芯基板，容纳在基板中的电子部件，形成在基板的表面上并且包括层间绝缘层的第一累积结构和形成在基板的相对表面上的第二累积结构， 层间绝缘层。 基板包括具有多个树脂层的芯材部分，形成在芯部的第一表面上的第一导电层和形成在芯部的第二表面上的第二导电层，芯部具有通过树脂层的开口并容纳 第一结构的绝缘层被定位成使得芯部的开口被覆盖在第一表面上，并且第二结构的绝缘层被定位成使得芯部的开口被覆盖在第二表面上 。

公开(公告)号：US09155196B2

公开(公告)日：2015-10-06

申请号：US14290193

申请日：2014-05-29

Applicant: IBIDEN CO., LTD.

Inventor： Haruhiko Morita

IPC: H05K1/16 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K1/165 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0225 ,  H05K1/0366 ,  H05K1/116 ,  H05K3/244 ,  H05K3/4602 ,  H05K2201/0191 ,  H05K2201/0293 ,  H05K2201/0347 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/09136 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/09836

Abstract: A wiring board includes a substrate having a laminated-inductor forming portion and including multiple first insulation layers and a second insulation layer formed on a first side of the first insulation layers such that the first insulation layers have the laminated-inductor forming portion, and a planar conductor formed on the second insulation layer of the substrate and formed to shield electromagnetic force generated from the laminated-inductor forming portion of the substrate. The laminated-inductor forming portion of the substrate has multiple inductor patterns formed on the first insulation layers and multiple via conductors connecting the inductor patterns through the first insulation layers, and the inductor patterns include an uppermost inductor pattern formed between the second insulation layer and the first insulation layers such that the uppermost inductor pattern has a distance of 100 μm or more from the planar conductor.

Abstract translation: 布线基板包括具有层叠电感器形成部分并且包括多个第一绝缘层的基板和形成在第一绝缘层的第一侧上的第二绝缘层，使得第一绝缘层具有层叠电感器形成部分，以及 形成在基板的第二绝缘层上并形成以屏蔽从基板的层叠电感器形成部分产生的电磁力的平面导体。 衬底的层叠电感器形成部分具有形成在第一绝缘层上的多个电感器图案和通过第一绝缘层连接电感器图案的多个通孔导体，并且电感器图案包括形成在第二绝缘层和 第一绝缘层，使得最上层的电感器图案与平面导体的距离为100μm以上。

公开(公告)号：US09113569B2

公开(公告)日：2015-08-18

申请号：US13414861

申请日：2012-03-08

Applicant: Yoshinori Takenaka

Inventor： Yoshinori Takenaka

IPC: H01F5/00 ,  H01F27/28 ,  H01F27/30 ,  H05K1/16 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K3/30 ,  H05K1/0233 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09672 ,  Y10T29/49021 ,  Y10T29/4913

Abstract: A wiring board includes a core structure having a first surface and a second surface on the opposite side of the first surface, a first buildup structure formed on the first surface of the core structure and including insulation layers, and a second buildup structure formed on the second surface of the core structure and including insulation layers and an inductor device. The insulation layers in the second buildup structure have the thicknesses which are thinner than the thicknesses of the insulation layers in the first buildup structure, and the inductor device in the second buildup structure is position on the second surface of the core structure and includes at least a portion of a conductive pattern formed in the core structure.

Abstract translation: 布线基板包括具有在第一表面的相对侧上的第一表面和第二表面的芯结构，形成在芯结构的第一表面上并包括绝缘层的第一堆积结构，以及形成在第一堆积结构上的第二堆积结构 芯结构的第二表面并包括绝缘层和电感器件。 第二堆积结构中的绝缘层具有比第一堆积结构中的绝缘层的厚度薄的厚度，并且第二堆叠结构中的电感器件位于芯结构的第二表面上并且至少包括 形成在芯结构中的导电图案的一部分。

公开(公告)号：US20150075851A1

公开(公告)日：2015-03-19

申请号：US14548725

申请日：2014-11-20

Applicant: IBIDEN CO., LTD.

Inventor： Masahiro KANEKO ,  Satoru KOSE ,  Hirokazu HIGASHI

IPC: H05K3/42 ,  H05K1/03 ,  H05K3/22 ,  H05K1/11

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract translation: 印刷电路板包括具有贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的第一表面上的导电电路，形成在层间树脂绝缘层的穿透孔中并与导电 电路，形成在填充的通路导体的第一表面上并具有无电解电镀结构的第一表面处理涂层结构和形成在填充通孔导体的第二表面上的第二表面处理涂层结构，该第二表面处理涂层结构相对于 涉及第一表面处理涂层结构并具有化学镀层结构。 填充的通孔导体包括形成在穿透孔的侧壁上的第一导电层和填充穿透孔的电镀材料，第一表面处理涂层结构的厚度与第二表面处理涂层的厚度不同 结构体。