公开(公告)号：US07205668B2

公开(公告)日：2007-04-17

申请号：US11285334

申请日：2005-11-22

Applicant: Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

Inventor： Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

IPC: H01L23/04 ,  H01L23/02 ,  H05K7/06

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09836

Abstract: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.

Abstract translation: 多层印刷电路板（PCB）包括第一布线层，第一布线层之上的中间层，中间层上方的第二布线层和形成在中间层和第二布线层中的倾斜孔。 该制造方法包括以下步骤：在第一布线层上形成第一布线层并形成第一布线，在第一布线层上形成中间层，在中间层上形成第二布线层，在中间层形成倾斜孔 层和第二线层，其中倾斜通孔的方向不与第一和第二线层正交，通过蚀刻方法在第二线层上形成第二布线，并且在通孔中形成电镀层以连接 第一布线和第二布线。

公开(公告)号：US20070049130A1

公开(公告)日：2007-03-01

申请号：US11510591

申请日：2006-08-28

Applicant: Toshiya Kojima ,  Gentaro Furukawa

Inventor： Toshiya Kojima ,  Gentaro Furukawa

IPC: H01R13/40

CPC classification number: H05K3/06 ,  B41J2/14233 ,  B41J2002/14459 ,  B41J2002/14491 ,  B41J2202/18 ,  H05K1/0265 ,  H05K3/041 ,  H05K3/061 ,  H05K3/107 ,  H05K3/244 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2201/09827 ,  H05K2201/09836 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/1527

Abstract: The wiring substrate comprises: a recess section and a projecting section formed on at least one surface of the wiring substrate; and wires formed on both the recess section and the projecting section.

Abstract translation: 布线基板包括：形成在布线基板的至少一个表面上的凹部和突出部; 以及形成在所述凹部和所述突出部两者上的线。

公开(公告)号：US20060131283A1

公开(公告)日：2006-06-22

申请号：US11016440

申请日：2004-12-17

Applicant: Jeffrey Hall ,  Yogendra Ranade ,  Sarathy Rajagopalan

Inventor： Jeffrey Hall ,  Yogendra Ranade ,  Sarathy Rajagopalan

IPC: B23K26/38

CPC classification number: H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/48227 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0047 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T408/86

Abstract: A method and apparatus for making angled vias in an integrated circuit package substrate includes providing an integrated circuit package substrate having an upper surface and a lower surface. A first position is selected for a first via opening on the upper surface of the package substrate, and a second position is selected for a second via opening on the lower surface of the package substrate. A selected non-vertical angle is determined for forming an angled via through the first position and the second position. The angled via is formed through the first position and the second position at the selected non-vertical angle.

Abstract translation: 一种用于在集成电路封装衬底中形成倾斜通孔的方法和装置包括提供具有上表面和下表面的集成电路封装衬底。 对于封装基板的上表面上的第一通孔，选择第一位置，并且在封装基板的下表面上选择用于第二通孔的第二位置。 确定所选择的非垂直角以形成通过第一位置和第二位置的成角度的通孔。 成角度的通孔以选定的非垂直角通过第一位置和第二位置形成。

公开(公告)号：US20060046537A1

公开(公告)日：2006-03-02

申请号：US10927760

申请日：2004-08-27

Applicant: Chin Chong ,  Choon Lee

Inventor： Chin Chong ,  Choon Lee

IPC: H01R12/00

CPC classification number: H01R12/526 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/4922

Abstract: Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first terminal is disposed on the first surface of the dielectric portion for connection to a first electronic component. A second terminal is disposed on the second surface of the dielectric portion for connection to a second electronic component. The apparatus further includes a passage extending through the dielectric portion along a longitudinal axis oriented at an oblique angle relative to the first surface. The passage is at least partially filled with conductive material electrically connecting the first terminal to the second terminal.

公开(公告)号：US20050251777A1

公开(公告)日：2005-11-10

申请号：US10839488

申请日：2004-05-05

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: G06F17/50 ,  H01L21/44 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC classification number: H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/429 ,  H05K2201/09836

Abstract: A method and structure are provided for implementing enhanced electronic packaging and printed circuit board (PCB) layout. A diagonal via is formed at a selected angle between a first side and an opposite second side of a printed circuit board at a selected printed circuit board location. The diagonal via is plated with an electrically conductive material. Diagonal vias are used to interconnect between a high-density pitch on the first side and a larger pitch on the opposite second side of the printed circuit board. The diagonal vias can be used to selectively interconnect electrical patterns of selected layers and eliminate the use of blind and buried vias.

Abstract translation: 提供了一种用于实现增强型电子封装和印刷电路板（PCB）布局的方法和结构。 在所选择的印刷电路板位置处，在印刷电路板的第一侧和相对的第二侧之间以选定的角度形成对角通孔。 对角通孔镀有导电材料。 对角通孔用于在第一侧上的高密度间距和在印刷电路板的相对的第二侧上的较大节距之间进行互连。 对角通孔可用于选择性地互连所选层的电气图案，并消除使用盲孔和埋孔。

公开(公告)号：US20050108876A1

公开(公告)日：2005-05-26

申请号：US10723269

申请日：2003-11-26

Applicant: Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

Inventor： Gaetan Mathieu ,  Igor Khandros ,  Carl Reynolds

IPC: G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  H05K3/30 ,  H05K3/42 ,  H05K3/00 ,  H05K13/00

CPC classification number: H05K3/42 ,  G01R1/06711 ,  G01R1/07307 ,  G01R3/00 ,  H05K3/308 ,  H05K2201/09836 ,  H05K2203/0338 ,  Y10T29/49117 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49194

Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

Abstract translation: 提供了用于制造用于插入和连接连接器探针的电镀通孔的方法。 在第一种方法中，通过将弯曲的可蚀刻线接合到第一衬底上形成弯曲的电镀通孔，用不可蚀刻的导电材料镀覆电线，用电介质材料包住电镀线以形成第二衬底， 衬底以暴露可蚀刻线，并蚀刻电线以留下镀通孔。 在第二种方法中，首先将涂覆有第一可蚀刻层的线接合到衬底上，然后将第二不可蚀刻镀层施加在第一层上，并且第一层被蚀刻掉，从而通过设置在内部的布线的孔通过电镀。 在第三实施例中，掩模材料层最初沉积在衬底上并被蚀刻以形成填充有牺牲填充材料的孔，然后去除掩模材料，电镀填充材料，进行研磨以除去一些电镀 露出填充材料，然后将填充材料蚀刻掉，留下电镀的连接孔。 探针可以附着到电镀通孔或连接孔，以产生弹性弹簧触点，以形成晶片探针卡组件。 通过将涂覆有电镀材料的扭转牺牲线支撑在基板中，并且随后蚀刻掉线来形成扭曲管镀通孔结构。

公开(公告)号：US06841882B2

公开(公告)日：2005-01-11

申请号：US10293564

申请日：2002-11-14

Applicant: Ray Chien

Inventor： Ray Chien

IPC: H01L23/498 ,  H05K3/34 ,  H05K3/40 ,  H01L23/00 ,  H01R12/00 ,  H01R13/40 ,  H01K4/58

CPC classification number: H05K3/4038 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2203/0235 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/00

Abstract: An elastomer interposer employed between a package and a printed circuit board and the method of manufacturing the same are disclosed. The elastomer interposer includes an elastomer, a plurality of conductive wires, Cu pads, solder resistant blocks and Ni/Au plated pads. The elastomer has two contact surfaces. The conductive wires are arranged inside the elastomer at a certain interval and tilted toward one of the contact surfaces with an inclined angle. The Cu pads are formed on both of the surfaces at a space, and electrically connected to the corresponding conductive wires. Also, the Ni/Au plated pads are formed over the Cu pads.

Abstract translation: 公开了一种在封装和印刷电路板之间采用的弹性体插入件及其制造方法。 弹性体插入件包括弹性体，多根导线，铜焊盘，阻焊块和Ni / Au电镀垫。 弹性体具有两个接触表面。 导线以一定的间隔配置在弹性体的内侧，以倾斜角朝向其中一个接触面倾斜。 Cu焊盘在空间的两个表面上形成，并且电连接到相应的导线。 此外，Ni / Au电镀焊盘形成在Cu焊盘上。

公开(公告)号：US06467692B1

公开(公告)日：2002-10-22

申请号：US09355328

申请日：1999-10-18

Applicant: Thomas Tarantino ,  Yahya Haghiri-Tehrani

Inventor： Thomas Tarantino ,  Yahya Haghiri-Tehrani

IPC: G06K1906

CPC classification number: G06K19/0775 ,  G06K19/07749 ,  H05K1/0268 ,  H05K1/183 ,  H05K3/0044 ,  H05K3/28 ,  H05K3/305 ,  H05K3/321 ,  H05K3/4007 ,  H05K2201/09836 ,  H05K2203/0207 ,  H05K2203/0228

Abstract: The invention relates to a card-shaped data carrier comprising a card body (1) having an antenna (3), and a chip module (2) containing an integrated circuit (10) and inserted into a gap (5) in the card body (1). The electric connection between the antenna (3) and the chip module (2) is effected via depressions (11) in the terminals (4) of the antenna (3). For producing the inventive data carrier one provides the card body (1), in which the antenna (3) is at least partly embedded, with a gap (5). The terminals (4) of the antenna (3) are exposed by removing the superjacent card material whereby part of the material forming the terminals (4) is also removed. The chip module (2) is inserted into the gap (5) and for example glued to the card body (1) with a thermally activable adhesive (6), an electric connection being formed between the chip module (2) and the antenna (3) for example by means of a conductive adhesive (7) previously applied to the exposed terminals (4) of the antenna (3). In the preferred embodiment the material removal on the terminals (4) of the antenna (3) is effected such that a bevel arises.

Abstract translation: 本发明涉及一种卡形数据载体，其包括具有天线（3）的卡体（1）和包含集成电路（10）并插入卡体内的间隙（5）中的芯片模块（2） （1）。 天线（3）和芯片模块（2）之间的电连接通过天线（3）的端子（4）中的凹陷（11）进行。 为了制造本发明的数据载体，提供了具有间隙（5）的天线（3）至少部分地嵌入其中的卡体（1）。 天线（3）的端子（4）通过去除上述相邻的卡材料而被暴露，由此形成端子（4）的材料的一部分也被去除。 芯片模块（2）插入到间隙（5）中，例如用可热激活的粘合剂（6）粘合到卡体（1）上，在芯片模块（2）和天线（2）之间形成电连接 3），例如通过先前施加到天线（3）的暴露端子（4）的导电粘合剂（7）。 在优选实施例中，实现天线（3）的端子（4）上的材料移除，从而产生斜面。

公开(公告)号：US20020145171A1

公开(公告)日：2002-10-10

申请号：US10117614

申请日：2002-04-05

Applicant: Sharp Kabushiki Kaisha

Inventor： Koichi Miyachi ,  Yoshihiro Izumi ,  Hiroshi Gohda

IPC: H01L027/14 ,  H01L031/00

CPC classification number: G02B6/125 ,  G02B6/43 ,  G02B2006/12038 ,  G02B2006/12178 ,  H01L2924/0002 ,  H05K3/403 ,  H05K3/4611 ,  H05K2201/0326 ,  H05K2201/09154 ,  H05K2201/0919 ,  H05K2201/09836 ,  H01L2924/00

Abstract: The circuit structure of the present invention has a plurality of conductive path layers and at least one interlayer isolating layer formed between the plurality of conductive path layers. Each of the plurality of conductive path layers has at least one conductive path capable of transmitting light or electricity therethrough. Each of a plurality of input/output (I/O) sections is connected to any one of the plurality of conductive paths. Each of the plurality of conductive path layers has a first laminated structure that includes a plurality of first conductive layers and at least one first isolating layer formed therebetween. The interlayer isolating layer has a second laminated structure that includes a plurality of second isolating layers and at least one second conductive layer formed therebetween.

Abstract translation: 本发明的电路结构具有形成在多个导电路径层之间的多个导电路径层和至少一个层间隔离层。 多个导电路径层中的每一个具有能够透过光或电的至少一个导电路径。 多个输入/输出（I / O）部分中的每一个连接到多个导电路径中的任何一个。 多个导电路径层中的每一个具有包括多个第一导电层和在它们之间形成的至少一个第一隔离层的第一层叠结构。 层间绝缘层具有包括多个第二隔离层和在其间形成的至少一个第二导电层的第二层叠结构。

公开(公告)号：US06459039B1

公开(公告)日：2002-10-01

申请号：US09597906

申请日：2000-06-19

Applicant: Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

Inventor： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

IPC: H05K102

CPC classification number: H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/113 ,  H05K3/3436 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2224/0401

Abstract: An electronic package assembly for electrical interconnection between two electronic modules having differing conductive array parameters is disclosed. The electronic package assembly includes two electronic modules, providing between the two electronic modules an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer of the electronic package assembly, with the conductors including a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection. A conductive matrix surrounds the conductors of the interposer of the electronic package assembly. The first set of conductive arrays includes the same conductive array parameters as a first electronic module and the second set of conductive arrays includes the same conductive array parameters as a second electronic module.

Abstract translation: 公开了一种用于具有不同导电阵列参数的两个电子模块之间的电互连的电子封装组件。 电子封装组件包括两个电子模块，在两个电子模块之间提供具有顶表面和底表面的插入件; 具有在顶表面上具有第一导电阵列参数的第一组导电阵列和在底表面上具有第二导电阵列参数的第二组导电阵列，所述第二导电阵列和第一导电阵列具有不同的参数。 多个导体横穿电子封装组件的插入件的厚度，其中导体包括任选涂覆有电介质材料的导电材料，导体在第一导电阵列处具有第一端，在第二导电阵列处具有第二端 由此连接其中的第一和第二导电阵列的导体适于空间转换不同的参数以提供电互连。 导电矩阵围绕电子封装组件的插入件的导体。 第一组导电阵列包括与第一电子模块相同的导电阵列参数，第二组导电阵列包括与第二电子模块相同的导电阵列参数。