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公开(公告)号：US20180033719A1
公开(公告)日：2018-02-01
申请号：US15725144
申请日：2017-10-04
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Li-Chuan TSAI , Chih-Cheng LEE
IPC: H01L23/498 , H01L21/48 , H05K1/02 , H05K3/36 , H05K3/22 , H05K3/00 , H05K1/18 , H05K1/11 , H05K3/40 , H01L23/00
CPC classification number: H01L23/49838 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L24/17 , H01L2224/16227 , H01L2924/15153 , H01L2924/15313 , H01L2924/19105 , H05K1/0266 , H05K1/0298 , H05K1/111 , H05K1/115 , H05K1/181 , H05K1/183 , H05K3/0017 , H05K3/0026 , H05K3/0047 , H05K3/22 , H05K3/36 , H05K3/40 , H05K3/4682 , H05K3/4697 , H05K2201/0158 , H05K2201/09472 , H05K2201/09527 , H05K2201/10204 , H05K2203/166 , Y02P70/611
Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.
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公开(公告)号：US20170373269A1
公开(公告)日：2017-12-28
申请号：US15609635
申请日：2017-05-31
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Taean SEO , Jinhwan CHOI , Junghun LEE
CPC classification number: H01L51/5237 , G09F9/301 , H01L27/3223 , H01L27/3276 , H01L27/3293 , H01L51/0097 , H01L2251/5338 , H05K1/0201 , H05K1/111 , H05K1/181 , H05K7/20954 , H05K2201/10204
Abstract: A rollable display apparatus includes a flexible panel including a main panel with a display and a dummy panel with a wire connected to the display, a housing to accommodate the flexible panel, a rotatable rolling drum in the housing and coupled to a first end of the flexible panel, a supporting base moveable into and out of the housing and coupled to a second end of the flexible panel, and a printed circuit board connected to the second end of the flexible panel, the printed circuit board being on the supporting base.
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公开(公告)号：US20170047295A1
公开(公告)日：2017-02-16
申请号：US15298234
申请日：2016-10-20
Applicant: Powertech Technology Inc.
Inventor： Yuan-Fu Lan , Hsien-Wen Hsu
IPC: H01L23/00 , H05K1/18 , H01L23/498
CPC classification number: H01L23/562 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H05K1/18 , H05K2201/10204
Abstract: A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.
Abstract translation: 载体衬底包括绝缘封装，第一导电图案，第二导电图案，至少一个第一虚设图案和至少一个第二虚设图案。 载体基板具有第一布局区域和第二布局区域。 第一导电图案和第一虚设图案位于第一布局区域中。 第二导电图案和第二虚设图案位于第二布局区域中。 第一和第二导电图案以及第一和第二虚设图案嵌入在绝缘封装中。 绝缘封装暴露了第一和第二导电图案以及第一和第二虚拟图案的顶表面。 第一虚设图案和第二虚设图案与第一导电图案和第二导电图案绝缘。 面向第二虚拟图案的第一伪图案的边缘轮廓是非线性的。
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公开(公告)号：US09485854B2
公开(公告)日：2016-11-01
申请号：US14464279
申请日：2014-08-20
Applicant: Intel Corporation
Inventor： Shaowu Huang , Kai Xiao , Beom-Taek Lee , Boping Wu , Xiaoning Ye
IPC: H05K1/02 , H01P3/08 , H01P11/00 , H05K1/09 , H05K3/30 , H05K1/18 , G06F1/16 , H01P1/26 , H01P5/16 , H04L25/03
CPC classification number: H05K1/023 , G06F1/16 , H01P1/268 , H01P3/08 , H01P5/16 , H01P11/003 , H01R12/737 , H01R13/6461 , H04L25/03006 , H05K1/0216 , H05K1/0231 , H05K1/0243 , H05K1/0246 , H05K1/0268 , H05K1/09 , H05K1/181 , H05K3/22 , H05K3/303 , H05K3/4007 , H05K2201/10159 , H05K2201/10204
Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。
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45.发明申请公开(公告)号：US20160270219A1
公开(公告)日：2016-09-15
申请号：US15033836
申请日：2014-10-24
Applicant: INGENICO GROUP
Inventor： Stephane Pavageau , Xavier Lambert
CPC classification number: H05K1/0284 , B23K1/0016 , B23K2101/42 , G06F21/86 , G06K7/0091 , H05K1/0275 , H05K3/10 , H05K3/1241 , H05K3/1275 , H05K3/143 , H05K3/245 , H05K3/34 , H05K2201/09409 , H05K2201/09781 , H05K2201/098 , H05K2201/10204 , H05K2203/0551
Abstract: A support is provided for fabrication of an electronic device. The support includes at least one component to be protected and at least one three-dimensional element of a height at least equal to a height of the electronic component. The three-dimensional element is disposed laterally opposite the at least one component to be protected. The three-dimensional element is chiefly constituted of a permanent assembling material.
Abstract translation: 提供了用于制造电子设备的支撑件。 支撑件包括至少一个待保护的部件和至少一个至少等于电子部件高度的高度的三维元件。 三维元件与要保护的至少一个部件横向相对设置。 三维元素主要由永久组装材料构成。
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Patent Agency Ranking
公开(公告)号：US20160057851A1
公开(公告)日：2016-02-25
申请号：US14464279
申请日：2014-08-20
Applicant: Intel Corporation
Inventor： Shaowu Huang , Kai Xiao , Beom-Taek Lee , Boping Wu , Xiaoning Ye
CPC classification number: H05K1/023 , G06F1/16 , H01P1/268 , H01P3/08 , H01P5/16 , H01P11/003 , H01R12/737 , H01R13/6461 , H04L25/03006 , H05K1/0216 , H05K1/0231 , H05K1/0243 , H05K1/0246 , H05K1/0268 , H05K1/09 , H05K1/181 , H05K3/22 , H05K3/303 , H05K3/4007 , H05K2201/10159 , H05K2201/10204
Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20150334850A1
公开(公告)日：2015-11-19
申请号：US14707295
申请日：2015-05-08
Applicant: NGK SPARK PLUG CO., LTD.
Inventor： Takahiro HAYASHI
CPC classification number: H05K3/28 , H05K1/0284 , H05K3/188 , H05K3/243 , H05K3/244 , H05K3/282 , H05K3/381 , H05K3/383 , H05K3/4007 , H05K3/46 , H05K3/4602 , H05K3/4661 , H05K2201/09409 , H05K2201/09536 , H05K2201/0959 , H05K2201/10204 , H05K2203/0307 , H05K2203/0574 , H05K2203/058 , H05K2203/0597 , H05K2203/0766 , Y10T29/49156
Abstract: A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.
Abstract translation: 根据本发明的制造布线基板的方法包括在第一绝缘层上形成包括连接端子的布线层的步骤; 在所述布线层和所述第一绝缘层上形成第二绝缘层的步骤; 通过图案化所述第二绝缘层而形成与所述第一绝缘层上的所述布线层分离的电绝缘的虚设部分的步骤; 在所述布线层上，所述虚拟部分上和所述第一绝缘层上形成第三绝缘层的步骤; 以及在所述第三绝缘层中形成用于暴露所述连接端子的开口的步骤，使得所述连接端子的上端部从所述第三绝缘层突出，并且所述连接端子的下端部嵌入所述第三绝缘层 。
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48.发明申请公开(公告)号：US20150242025A1
公开(公告)日：2015-08-27
申请号：US14191484
申请日：2014-02-27
Applicant: Ronald Steven Cok
Inventor： Ronald Steven Cok
CPC classification number: G06F3/044 , G06F1/16 , G06F3/0412 , G06F3/0416 , G06F3/042 , G06F3/046 , G06F3/047 , G06F2203/04103 , G06F2203/04107 , G06F2203/04111 , G06F2203/04112 , H05K1/0216 , H05K1/0296 , H05K2201/10204 , Y10T29/49105 , Y10T29/49117
Abstract: A method of making a micro-wire electrode structure includes providing a substrate having a surface. A plurality of first micro-wire electrodes spatially separated by first electrode gaps is located in a first layer in relation to the surface, each first micro-wire electrode including a plurality of electrically connected first micro-wires. A plurality of electrically isolated second micro-wire electrodes in a second layer is located in relation to the surface, the second layer at least partially different from the first layer and each second micro-wire electrode including a plurality of electrically connected second micro-wires. A plurality of first gap micro-wires is located in each first electrode gap, at least some of the first gap micro-wires located in a gap layer different from the first layer, the first gap micro-wires electrically isolated from the first micro-wires.
Abstract translation: 制造微线电极结构的方法包括提供具有表面的衬底。 通过第一电极间隙空间分隔的多个第一微线电极位于相对于表面的第一层中，每个第一微线电极包括多个电连接的第一微线。 第二层中的多个电隔离的第二微线电极相对于表面定位，第二层至少部分地不同于第一层，每个第二微线电极包括多个电连接的第二微线 。 多个第一间隙微细线位于每个第一电极间隙中，至少一些第一间隙微线位于不同于第一层的间隙层中，第一间隙微线与第一微缝隙电绝缘， 电线
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公开(公告)号：US20150242010A1
公开(公告)日：2015-08-27
申请号：US14191482
申请日：2014-02-27
Applicant: RONALD STEVEN COK
Inventor： RONALD STEVEN COK
CPC classification number: G06F3/044 , G06F1/16 , G06F3/0412 , G06F3/0416 , G06F3/042 , G06F3/046 , G06F3/047 , G06F2203/04103 , G06F2203/04107 , G06F2203/04111 , G06F2203/04112 , H05K1/0216 , H05K1/0296 , H05K2201/10204 , Y10T29/49105 , Y10T29/49117
Abstract: A micro-wire electrode structure includes a substrate having a surface. A plurality of first micro-wire electrodes spatially separated by first electrode gaps is located in a first layer in relation to the surface, each first micro-wire electrode including a plurality of electrically connected first micro-wires. A plurality of electrically isolated second micro-wire electrodes is located in a second layer in relation to the surface, the second layer at least partially different from the first layer. Each second micro-wire electrode includes a plurality of electrically connected second micro-wires. A plurality of first gap micro-wires is located in each first electrode gap, at least some of the first gap micro-wires located in a gap layer different from the first layer. The first gap micro-wires are electrically isolated from the first micro-wires.
Abstract translation: 微线电极结构包括具有表面的基板。 通过第一电极间隙空间分隔的多个第一微线电极位于相对于表面的第一层中，每个第一微线电极包括多个电连接的第一微线。 多个电隔离的第二微线电极相对于表面位于第二层中，第二层至少部分地不同于第一层。 每个第二微线电极包括多个电连接的第二微线。 多个第一间隙微细线位于每个第一电极间隙中，至少一些第一间隙微细线位于不同于第一层的间隙层中。 第一间隙微线与第一微线电隔离。
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公开(公告)号：US20150230332A1
公开(公告)日：2015-08-13
申请号：US14424831
申请日：2013-08-06
Applicant: Robert Bosch GmbH
Inventor： Tobias Stiefel
IPC: H05K1/02
CPC classification number: H05K1/0259 , H02K11/26 , H05K2201/10204
Abstract: Surge arrester for a an electric machine, comprising a dummy component (2) which is, compared to components on a circuit board (1) of the electric machine, mounted at the shortest distance from a discharge element (4) of the electric machine, the dummy component (2) being connected to earth potential in at least one terminal.
Abstract translation: 与电机的电路板（1）上的与电动机的排出元件（4）最短距离安装的部件相比，包括一个虚拟部件（2）的电动避雷器， 所述虚拟部件（2）在至少一个端子中连接到地电位。
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