公开(公告)号：US11908696B2

公开(公告)日：2024-02-20

申请号：US17569870

申请日：2022-01-06

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: H01L21/285 ,  H01L21/768 ,  C23C14/56 ,  C23C14/14 ,  C23C14/24 ,  C23C14/06

CPC classification number: H01L21/2855 ,  C23C14/0641 ,  C23C14/14 ,  C23C14/24 ,  C23C14/56 ,  H01L21/76829 ,  H01L21/76876

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US11289342B2

公开(公告)日：2022-03-29

申请号：US16901210

申请日：2020-06-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US11205589B2

公开(公告)日：2021-12-21

申请号：US16594057

申请日：2019-10-06

Applicant: APPLIED MATERIALS, INC.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Srinivas D Nemani ,  Ellie Yieh

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285 ,  H01L21/67 ,  C23C14/58 ,  H01L21/3213 ,  C23C14/16

Abstract: Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.

公开(公告)号：US20210384036A1

公开(公告)日：2021-12-09

申请号：US17339454

申请日：2021-06-04

Applicant: Applied Materials, Inc.

Inventor： Ilanit Fisher ,  Chi-Chou Lin ,  Kedi Wu ,  Wen Ting Chen ,  Shih Chung Chen ,  Srinivas Gandikota ,  Mandyam Sriram ,  Chenfei Shen ,  Naomi Yoshida ,  He Ren

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/14 ,  C23C16/04

Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.

公开(公告)号：US11094588B2

公开(公告)日：2021-08-17

申请号：US16562091

申请日：2019-09-05

Applicant: Applied Materials, Inc.

Inventor： Shi You ,  He Ren ,  Mehul B. Naik

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

Abstract: Embodiments of the present disclosure generally relate an interconnect structure formed on a substrate and a method of forming the interconnect structure thereon. In one embodiment, a method of forming an interconnect structure includes forming an opening comprising a via and a trench in an insulating structure formed on a substrate, forming a first passivation layer in the opening, removing a portion of the first passivation layer from the opening, and selectively depositing a first metal containing material in the via.

公开(公告)号：US10916433B2

公开(公告)日：2021-02-09

申请号：US16366539

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Maximillian Clemons ,  Mei-Yee Shek ,  Minrui Yu ,  Bencherki Mebarki ,  Mehul B. Naik ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L21/285 ,  H01L21/32 ,  H01L21/768 ,  C23C14/04 ,  C23C14/06 ,  C23C14/35 ,  C23C14/22 ,  C23C14/58 ,  H01L29/45 ,  H01L21/3205 ,  H01L23/532

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

公开(公告)号：US10388533B2

公开(公告)日：2019-08-20

申请号：US15988854

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Minrui Yu ,  Mehul B. Naik

IPC: H01L23/40 ,  H01L21/285 ,  H01L21/67 ,  H01L23/532 ,  H01L21/768 ,  C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  H01J37/34

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

公开(公告)号：US20170309515A1

公开(公告)日：2017-10-26

申请号：US15137245

申请日：2016-04-25

Applicant: APPLIED MATERIALS, INC.

Inventor： He Ren ,  Jie Zhou ,  Guannan Chen ,  Michael W. Stowell ,  Bencherki Mebarki ,  Mehul Naik ,  Srinivas D. Nemani ,  Nikolaos Bekiaris ,  Zhiyuan Wu

IPC: H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/28556 ,  H01L21/76877 ,  H01L23/53209

Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

公开(公告)号：US09640424B2

公开(公告)日：2017-05-02

申请号：US15084104

申请日：2016-03-29

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik

IPC: H01L21/764 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3213

CPC classification number: H01L21/76802 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32136 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

公开(公告)号：US09514953B2

公开(公告)日：2016-12-06

申请号：US14541978

申请日：2014-11-14

Applicant: Applied Materials, Inc.

Inventor： Chia-Ling Kao ,  Sean Kang ,  Jeremiah T. Pender ,  Srinivas D. Nemani ,  He Ren ,  Mehul Naik

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。