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    METAL SELENIDE AND METAL TELLURIDE THIN FILMS FOR SEMICONDUCTOR DEVICE APPLICATIONS
    52.
    发明申请
    METAL SELENIDE AND METAL TELLURIDE THIN FILMS FOR SEMICONDUCTOR DEVICE APPLICATIONS 有权
    金属硒化物和金属薄膜薄膜用于半导体器件应用

    公开(公告)号：US20160372543A1

    公开(公告)日：2016-12-22

    申请号：US14741246

    申请日：2015-06-16

    Applicant: ASM IP Holding B.V.

    Inventor： Qi Xie ,  Fu Tang ,  Michael Eugene Givens ,  Jan Willem Maes

    IPC: H01L29/06 ,  H01L29/51 ,  H01L29/40

    CPC classification number: H01L29/517 ,  H01L21/28255 ,  H01L21/28264 ,  H01L29/513 ,  H01L29/66568

    Abstract: In some aspects, methods of forming a metal selenide or metal telluride thin film are provided. According to some methods, a metal selenide or metal telluride thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase selenium or tellurium reactant. In some aspects, methods of forming three-dimensional architectures on a substrate surface are provided. In some embodiments, the method includes forming a metal selenide or metal telluride interface layer between a substrate and a dielectric. In some embodiments, the method includes forming a metal selenide or metal telluride dielectric layer between a substrate and a conductive layer.

    Abstract translation: 在一些方面，提供了形成金属硒化物或金属碲化物薄膜的方法。 根据一些方法，金属硒化物或金属碲化物薄膜在循环沉积过程中在反应空间中沉积在基底上，其中至少一个循环包括交替地并且顺序地将基底与第一气相金属反应物接触， 气相硒或碲反应物。 在一些方面，提供了在衬底表面上形成三维结构的方法。 在一些实施方案中，该方法包括在基材和电介质之间形成金属硒化物或金属碲化物界面层。 在一些实施方案中，该方法包括在衬底和导电层之间形成金属硒化物或金属碲化物电介质层。

    METHODS FOR SEMICONDUCTOR PASSIVATION BY NITRIDATION
    53.
    发明申请
    METHODS FOR SEMICONDUCTOR PASSIVATION BY NITRIDATION 有权
    通过硝化的半导体钝化方法

    公开(公告)号：US20160358772A1

    公开(公告)日：2016-12-08

    申请号：US14729510

    申请日：2015-06-03

    Applicant: ASM IP Holding B.V.

    Inventor： Qi Xie ,  Fu Tang ,  Michael Givens ,  Petri Raisanen ,  Jan Willem Maes

    IPC: H01L21/02 ,  H01L29/10 ,  H01L29/20 ,  H01L23/31 ,  H01L29/16

    CPC classification number: H01L21/02247 ,  H01L21/02112 ,  H01L21/02205 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/2807 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/518

    Abstract: In some embodiments, a semiconductor surface having a high mobility semiconductor may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD.

    Abstract translation: 在一些实施方案中，具有高迁移率半导体的半导体表面可以有效地通过氮化钝化，优选使用肼，肼衍生物或其组合。 该表面可以是晶体管沟道区的半导体表面。 在一些实施例中，在半导体表面处形成半导体表面氧化物层，并且通过在表面形成半导体氮氧化物层来实现钝化，其中氮化对表面氧化物产生氮以形成氧氮化物层。 半导体氧化物层可以通过原子层沉积（ALD）沉积，并且氮化也可以作为ALD的一部分进行。

    METHOD OF MAKING A WIRE-BASED SEMICONDUCTOR DEVICE
    54.
    发明申请
    METHOD OF MAKING A WIRE-BASED SEMICONDUCTOR DEVICE 有权
    制造基于线路的半导体器件的方法

    公开(公告)号：US20150214301A1

    公开(公告)日：2015-07-30

    申请号：US14678301

    申请日：2015-04-03

    Applicant: ASM IP Holding B.V.

    Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0254 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/057 ,  Y10S977/89 ,  Y10S977/938

    Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

    Abstract translation: 在一些实施例中，制造方法形成诸如晶体管的半导体器件。 在半导体衬底上形成电介质叠层。 堆叠包括由多个间隔层之一隔开的多个电介质层。 多个间隔层中的每一个由与多个电介质层的紧邻层不同的材料形成。 通过多个介电层和多个间隔层形成垂直延伸的孔。 通过进行外延沉积来填充孔，其中材料填充形成线的孔。 导线被掺杂，并且三个电介质层被顺序地移除并被导电材料代替，由此形成上部和下部接触线和上部和下部触点之间的栅极。 导线可以用作晶体管的沟道区。

    CYCLIC ALUMINUM NITRIDE DEPOSITION IN A BATCH REACTOR
    56.
    发明申请
    CYCLIC ALUMINUM NITRIDE DEPOSITION IN A BATCH REACTOR 有权
    循环反应器中的氮化铝沉淀

    公开(公告)号：US20140357090A1

    公开(公告)日：2014-12-04

    申请号：US13907718

    申请日：2013-05-31

    Applicant: ASM IP Holding B.V.

    Inventor： Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Peter Zagwijn ,  Hessel Sprey ,  Cornelius A. van der Jeugd ,  Marinus Josephus de Blank ,  Robin Roelofs ,  Qi Xie ,  Jan Willem Maes

    IPC: H01L21/02

    CPC classification number: H01L21/02178 ,  C23C16/303 ,  C23C16/45525 ,  C23C16/4583 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003

    Abstract: A process for depositing aluminum nitride is disclosed. The process comprises providing a plurality of semiconductor substrates in a batch process chamber and depositing an aluminum nitride layer on the substrates by performing a plurality of deposition cycles without exposing the substrates to plasma during the deposition cycles. Each deposition cycle comprises flowing an aluminum precursor pulse into the batch process chamber, removing the aluminum precursor from the batch process chamber, and removing the nitrogen precursor from the batch process chamber after flowing the nitrogen precursor and before flowing another pulse of the aluminum precursor. The process chamber may be a hot wall process chamber and the deposition may occur at a deposition pressure of less than 1 Torr.

    Abstract translation: 公开了一种沉积氮化铝的方法。 该方法包括在间歇处理室中提供多个半导体衬底，并且通过在沉积循环期间不使衬底暴露于等离子体，通过执行多个沉积循环在衬底上沉积氮化铝层。 每个沉积循环包括将铝前体脉冲流入分批处理室，从分批处理室中除去铝前体，以及在氮气前体流动之后并且在流过铝前体的另一个脉冲之前从分批处理室中除去氮前体。 处理室可以是热壁处理室，并且沉积可以在小于1托的沉积压力下进行。

    METHOD OF MAKING A RESISTIVE RANDOM ACCESS MEMORY DEVICE
    57.
    发明申请
    METHOD OF MAKING A RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权
    制造电阻随机访问存储器件的方法

    公开(公告)号：US20140322885A1

    公开(公告)日：2014-10-30

    申请号：US13872932

    申请日：2013-04-29

    Applicant: ASM IP Holding B.V.

    Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes ,  Michael Givens ,  Petri Raisanen

    IPC: H01L45/00

    CPC classification number: H01L45/1616 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146

    Abstract: A method for forming a resistive random access memory (RRAM) device is disclosed. The method comprises forming a first electrode, forming a resistive switching oxide layer comprising a metal oxide by thermal atomic layer deposition (ALD) and forming a second electrode by thermal atomic layer deposition (ALD), where the resistive switching layer is interposed between the first electrode and the second electrode. Forming the resistive switching oxide may be performed without exposing a surface of the switching oxide layer to a surface-modifying plasma treatment after depositing the metal oxide.

    Abstract translation: 公开了一种形成电阻随机存取存储器（RRAM）装置的方法。 该方法包括形成第一电极，通过热原子层沉积（ALD）形成包括金属氧化物的电阻式切换氧化物层，并通过热原子层沉积（ALD）形成第二电极，其中电阻式开关层介于第一 电极和第二电极。 可以在沉积金属氧化物之后，进行电阻式开关氧化物的形成而不使开关氧化物层的表面暴露于表面改性等离子体处理。

    METHOD OF MAKING A WIRE-BASED SEMICONDUCTOR DEVICE
    58.
    发明申请
    METHOD OF MAKING A WIRE-BASED SEMICONDUCTOR DEVICE 有权
    制造基于线路的半导体器件的方法

    公开(公告)号：US20140030859A1

    公开(公告)日：2014-01-30

    申请号：US14045680

    申请日：2013-10-03

    Applicant: ASM IP Holding B.V.

    Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

    IPC: H01L21/8238 ,  H01L21/02

    CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0254 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/057 ,  Y10S977/89 ,  Y10S977/938

    Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

    Abstract translation: 在一些实施例中，制造方法形成诸如晶体管的半导体器件。 在半导体衬底上形成电介质叠层。 堆叠包括由多个间隔层之一隔开的多个电介质层。 多个间隔层中的每一个由与多个电介质层的紧邻层不同的材料形成。 通过多个介电层和多个间隔层形成垂直延伸的孔。 通过进行外延沉积来填充孔，其中材料填充形成线的孔。 导线被掺杂，并且三个电介质层被顺序地移除并被导电材料代替，由此形成上部和下部接触线和上部和下部触点之间的栅极。 导线可以用作晶体管的沟道区。

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