公开(公告)号：US20180138146A1

公开(公告)日：2018-05-17

申请号：US15354291

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07001 ,  H01L2924/07025 ,  H01L2924/0675 ,  H01L2924/00014

Abstract: A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.

公开(公告)号：US20160216731A1

公开(公告)日：2016-07-28

申请号：US14604531

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Khai Ern See ,  Damien Weng Kong Chong ,  Min Suet Lim ,  Ping Ping Ooi ,  Chu Aun Lim ,  Jimmy Huat Since Huang ,  Poh Tat Oh ,  Teong Keat Beh ,  Jackson Chung Peng Kong ,  Fern Nee Tan ,  Jenn Chuan Cheng

IPC: G06F1/16 ,  H05K1/18 ,  G06F1/18 ,  G06F13/38

CPC classification number: G06F1/163 ,  G06F1/16 ,  G06F1/1656 ,  G06F1/187 ,  G06F13/38 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

Abstract translation: 实施例一般涉及利用计算机在包装结构上的装置。 计算机的一个实施例包括基板; 一个或多个半导体器件，所述一个或多个半导体器件是直接芯片附着到所述衬底，所述一个或多个半导体器件包括中央处理单元（CPU）; 以及安装在基板上的一个或多个附加部件，其中计算机不包括I / O部件。

公开(公告)号：US12216306B1

公开(公告)日：2025-02-04

申请号：US18397148

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Surya Pratap Mishra ,  Shantanu Dattatraya Kulkarni ,  Min Suet Lim

IPC: F21V8/00 ,  G06F1/16 ,  H05B47/11

Abstract: An illuminated display screen bezel may provide improved user illumination when using a portable electronic device. The illuminated display screen bezel may include a series of LEDs built into the bezel, may include a light guide plate, or may include an extended display area at least partially covered by a controllable opaque layer. These lighting mechanisms may be dynamically controlled and adjusted with one or more smart control algorithms to suit different users. The improved image quality may be used to provide improved performance of image processing features, such as improving the ability of a videoconferencing program to create a virtual background or improving the ability of an AI system to perform image analysis. These lighting configurations may also be used for providing notification lights, automatic dimming based on detected ambient light, program-enhancing RGB lighting effects, mood lighting, and other lighting effects.

公开(公告)号：US12167530B2

公开(公告)日：2024-12-10

申请号：US17127407

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Jaejin Lee ,  James Panakkal ,  Min Suet Lim ,  Aiswarya M. Pious

IPC: H05K1/02 ,  H05K9/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to EMI shielding and thermal conduction without using any surface area of a PCB. Embodiments of the EMI shield may include a planar top, with one or more walls extending from the planar top to a bottom surface of the PCB, the PCB having a top surface disposed between the bottom surface of the PCB and the planar top. A ground of the PCB may electrically couple with the one or more walls. The bottom of the walls may couple with an EMI gasket applied to a bottom chassis to increase the volume of EMI shielding. Other embodiments may be described and/or claimed.

公开(公告)号：US20240334600A1

公开(公告)日：2024-10-03

申请号：US18739944

申请日：2024-06-11

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Rijo Kizhakkedathu Avarachan ,  Eng Huat Goh

IPC: H05K1/11 ,  H01L23/00 ,  H05K1/18 ,  H10B80/00

CPC classification number: H05K1/111 ,  H05K1/181 ,  H01L24/16 ,  H01L2224/16227 ,  H05K2201/10159 ,  H10B80/00

Abstract: Printed circuit boards including direct routing from integrated circuit packages are disclosed. An example substrate disclosed herein including a first contact pad array to receive an integrated circuit package, a second contact pad array to receive a memory die, the first contact pad array having a matching arrangement as the second contact pad array, and a layer including a plurality of interconnections extending between the first contact pad array and the second contact pad array.

公开(公告)号：US20240310881A1

公开(公告)日：2024-09-19

申请号：US18185505

申请日：2023-03-17

Applicant: Intel Corporation

Inventor： Jeffrey Ho ,  Shawn Mceuen ,  Min Suet Lim ,  Yew San Lim ,  Bruce Cheng

IPC: G06F1/16 ,  F16C11/04

CPC classification number: G06F1/1681 ,  F16C11/04 ,  E05D3/02 ,  E05D5/14 ,  E05Y2999/00

Abstract: Hinges for electronic devices are disclosed herein. An example hinge includes a bracket capable of being coupled to a first portion of the electrical device. The bracket has a barrel defining a first opening. The hinge also includes a shaft in the first opening. The shaft is rotatable in the first opening. The hinge further includes a sleeve capable of being inserted into a bore in a second portion of the electronic device. The sleeve defines a second opening to receive a portion of the shaft.

公开(公告)号：US20230395480A1

公开(公告)日：2023-12-07

申请号：US17834674

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Jeff Ku ,  Min Suet Lim ,  Yew San Lim ,  Twan Sing Loo

IPC: H01L23/498 ,  H05K3/34 ,  H01L21/48 ,  H05K1/11

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K1/115 ,  H05K2201/10734 ,  H05K2201/0154 ,  H05K2201/10303 ,  H01L21/4853

Abstract: A substrate to printed circuit board (PCB) interconnect with liquid metal and surface pins. A thin dielectric sheet with drilled openings is adjacent to the bottom of a system on chip or CPU package substrate. Holes in the dielectric sheet have a liquid metal (LM) therein, the holes correspond to landing metal pads on the package substrate. The PCB includes surface pins in an arrangement to match the LM filled holes. A pick and place assembly of the package substrate to the PCB can be done without needing a reflow step. A magnet ring can be positioned on the polyimide sheet and configured to pair with a metal plate on the PCB. Guideposts around the periphery of the package substrate may be used to assist in alignment during assembly.

公开(公告)号：US11822410B2

公开(公告)日：2023-11-21

申请号：US17732792

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G06F1/3203 ,  G06F1/3234 ,  H01L25/16 ,  G06N3/063 ,  H01L25/065 ,  G06F1/20 ,  H01L25/18 ,  G06N3/08 ,  G06N3/044

CPC classification number: G06F1/3203 ,  G06F1/206 ,  G06F1/3243 ,  G06F1/3275 ,  G06N3/063 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/18 ,  G06N3/044 ,  G06N3/08

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example integrated circuit (IC) package includes a computer processor unit (CPU) die, a memory die, inference engine circuitry within the CPU die, the inference engine circuitry to infer, based on a first machine learning model, a workload for at least one of the CPU die or the memory die, and power management engine circuitry within the CPU die, the power management engine circuitry distinct from the inference engine circuitry, the power management engine circuitry to adjust, based on a second machine learning model different than the first machine learning model, operational parameters associated with the at least one of the CPU die or the memory die, the inferred workload to be an input to the second machine learning model.

公开(公告)号：US11658127B2

公开(公告)日：2023-05-23

申请号：US16454423

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Khang Choong Yong ,  Boon Ping Koh ,  Wil Choon Song ,  Min Suet Lim

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/09

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a package substrate on a substrate, a die on the package substrate, and a conductive stiffener over the package substrate and the substrate. The conductive stiffener surrounds the package substrate, where the conductive stiffener has a top portion and a plurality of sidewalls, and where the top portion is directly disposed on the package substrate, and the sidewalls are vertically disposed on the substrate. The semiconductor package also includes the substrate that has a plurality of conductive pads, where the conductive pads are conductively coupled to a ground source. The conductive stiffener may conductively couple the package substrate to the conductive pads of the substrate. The top portion may have a cavity that surrounds the die, where the top portion is directly disposed on a plurality of outer edges of the package substrate.

公开(公告)号：US11652057B2

公开(公告)日：2023-05-16

申请号：US16405610

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Eng Huat Goh ,  Min Suet Lim ,  Robert Sankman ,  Telesphor Kamgaing ,  Wil Choon Song ,  Boon Ping Koh

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L25/0655

Abstract: Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.