公开(公告)号：US20140085846A1

公开(公告)日：2014-03-27

申请号：US13625406

申请日：2012-09-24

Applicant: Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H05K1/18 ,  B32B38/04 ,  B32B38/10 ,  H05K1/00

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

Abstract translation: 本说明书的实施例涉及制造微电子结构的领域。 微电子结构可以包括与轨迹路由结构分开形成的玻璃布线结构，其中玻璃布线结构以层叠或嵌入的形式结合到迹线布线基板中。 还公开了微电子封装的实施例，其包括设置在微电子衬底的玻璃布线结构附近并通过多个互连与微电子衬底耦合的至少一个微电子器件。 此外，公开了微电子结构的实施例，其包括嵌入微电子密封剂内的至少一个微电子器件，该微电子器件具有连接到微电子密封剂的玻璃布线结构和形成在玻璃布线结构上的迹线布线结构。

公开(公告)号：US08491834B2

公开(公告)日：2013-07-23

申请号：US13181572

申请日：2011-07-13

Applicant: Yuichi Iida ,  Yusuke Otsuka

Inventor： Yuichi Iida ,  Yusuke Otsuka

IPC: C04B33/32

CPC classification number: H05K1/167 ,  B32B18/00 ,  C04B2235/9607 ,  C04B2237/343 ,  C04B2237/562 ,  C04B2237/62 ,  C04B2237/68 ,  H05K1/0306 ,  H05K3/28 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2203/308

Abstract: A laminate type ceramic electronic component includes a thick film resistor and an overcoat layer so as to prevent defects such as delamination from being caused and to prevent the thick film resistor from being cracked after laser trimming, even when a method is adopted in which an unfired composite laminate is subjected to firing in such a way that an unfired ceramic laminate, an unfired thick film resistor, and an unfired overcoat layer are each integrally sintered. The unfired overcoat layer includes a glass ceramic material containing a ceramic and glass having substantially the same constituents and compositional ratio as those of the glass contained in the unfired ceramic layer. The respective glass ceramic materials constituting the unfired ceramic layer and the unfired overcoat layer are adjusted so that the ratio of a crystalline phase with a smaller coefficient of thermal expansion than the coefficient of thermal expansion of the fired ceramic layer is higher in the overcoat layer than in the ceramic layer.

Abstract translation: 叠层型陶瓷电子部件包括厚膜电阻器和外涂层，以便防止在产生分层之类的缺陷，并且防止厚膜电阻器在激光修整之后破裂，即使采用不熟悉的方法 将复合层叠体进行焙烧，使得未烧结的陶瓷层压体，未烧结的厚膜电阻器和未烧结的外涂层均被一体烧结。 未焙烧的外涂层包括含有陶瓷和玻璃的玻璃陶瓷材料，其具有与未焙烧陶瓷层中所含的玻璃的成分和组成比基本相同的成分和组成比。 调整构成未烧结的陶瓷层和未烧结的外涂层的各玻璃陶瓷材料，使得在外涂层中，具有比煅烧陶瓷层的热膨胀系数小的热膨胀系数的结晶相的比例高于 在陶瓷层中。

公开(公告)号：US20130078408A1

公开(公告)日：2013-03-28

申请号：US13699398

申请日：2011-05-28

Applicant: Noritaka Niino ,  Masaya Ochi

Inventor： Noritaka Niino ,  Masaya Ochi

IPC: H05K3/00 ,  B32B3/26 ,  H05K3/28 ,  B32B3/30

CPC classification number: H05K3/0052 ,  B32B3/263 ,  B32B3/30 ,  H01L23/13 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/285 ,  H05K2201/017 ,  H05K2201/0909 ,  H05K2201/09909 ,  H05K2203/107 ,  Y10T29/49124 ,  Y10T225/12 ,  Y10T428/15 ,  Y10T428/24488 ,  H01L2924/00

Abstract: A segmentable wiring board includes a ceramic base body, a conductor, a metal plating film and a glass layer, the glass layer having an upwardly-protruding convexity located on the metal plating film. The ceramic base body has a plurality of wiring substrate regions and dividing grooves located in boundaries among the plurality of wiring substrate regions. Moreover, the conductor is located in a periphery of each of the plurality of wiring substrate regions. Moreover, the metal plating film is located on the conductor. Further, the glass layer coveringly extends from an inner surface of each of the dividing grooves of the ceramic base body to the metal plating film.

Abstract translation: 可分割布线板包括陶瓷基体，导体，金属镀膜和玻璃层，玻璃层具有位于金属镀膜上的向上凸出的凸起。 陶瓷基体具有位于多个布线基板区域中的边界中的多个布线基板区域和分割槽。 此外，导体位于多个布线基板区域的每一个的周边。 此外，金属镀膜位于导体上。 此外，玻璃层从陶瓷基体的各分隔槽的内表面覆盖地延伸到金属镀膜。

公开(公告)号：US20120228014A1

公开(公告)日：2012-09-13

申请号：US13042578

申请日：2011-03-08

Applicant: Rabindra N. Das ,  Mark D. Poliks ,  Voya R. Markovich ,  Peter A. Moschak

Inventor： Rabindra N. Das ,  Mark D. Poliks ,  Voya R. Markovich ,  Peter A. Moschak

IPC: H05K1/16 ,  B05D5/12

CPC classification number: H05K1/162 ,  H01G4/33 ,  H01G4/38 ,  H05K1/0231 ,  H05K3/4608 ,  H05K2201/017 ,  H05K2201/0179

Abstract: A circuitized substrate for use in such electrical structures as information handling systems wherein the substrate includes a capacitive substrate as part thereof. The capacitive substrate includes a thin film layer of capacitive material strategically positioned on a conductive layer relative to added electrically conductive elements to in turn provide a plurality of internal capacitors within the final circuitized substrate during operation thereof. A method of making such a circuitized substrate is also provided.

Abstract translation: 一种用于诸如信息处理系统的电气结构中的电路化基板，其中所述基板包括作为其一部分的电容基板。 电容性衬底包括相对于添加的导电元件策略性地定位在导电层上的电容材料薄层，从而在其操作期间在最终电路化衬底内提供多个内部电容器。 还提供了制造这种电路化基板的方法。

公开(公告)号：US08257529B2

公开(公告)日：2012-09-04

申请号：US12539629

申请日：2009-08-12

Applicant: Yasutaka Sugimoto

Inventor： Yasutaka Sugimoto

IPC: C03B29/00

CPC classification number: H05K1/111 ,  C03C14/004 ,  H05K1/0306 ,  H05K3/285 ,  H05K3/4614 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2201/068 ,  H05K2201/09481 ,  H05K2201/099 ,  Y02P70/611 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A multilayer ceramic substrate includes an inner layer portion and surface portions that sandwich the inner layer portion in the stacking direction and have an increased transverse strength because of the surface layer portion having a thermal expansion coefficient less than that of the inner layer portion. At least one of the surface portions covers peripheries of main-surface conductive films arranged on a main surface of an inner portion so as to leave central portions of the main-surface conductive films exposed, so that the main-surface conductive films function as via conductors, thereby eliminating the need to provide a via conductor in the surface portions.

Abstract translation: 多层陶瓷基板包括内层部分和由于表面层部分的热膨胀系数小于内层部分的热膨胀系数而在层叠方向上夹着内层部分并具有增加的横向强度的表面部分。 表面部分中的至少一个覆盖布置在内部主表面上的主表面导电膜的周边，以使主表面导电膜的中心部分露出，使得主表面导电膜用作通孔 导体，从而不需要在表面部分中提供通孔导体。

公开(公告)号：US07564131B2

公开(公告)日：2009-07-21

申请号：US10453503

申请日：2003-06-04

Applicant: Jin Hyung Ryu ,  Sam Je Cho

Inventor： Jin Hyung Ryu ,  Sam Je Cho

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L23/12 ,  H01L23/15 ,  H05K3/34 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/3452 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/017 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package and method for package a semiconductor that has high reliability. A semiconductor package according to the present invention comprises a first substrate on which a circuit pattern and an electrode pad are formed; a second substrate which is adhered to the first substrate and on which a hole is formed; and a solder ball adhered to the electrode pad through the hole formed on the second substrate. Then, the second substrate is used as a solder resist. Accordingly, since the first substrate and the second substrate are formed of same material, the BGA package can be prevented from being cracked and being nonuniform when fired.

Abstract translation: 公开了一种具有高可靠性的用于封装半导体的半导体封装和方法。 根据本发明的半导体封装包括其上形成有电路图案和电极焊盘的第一基板; 第二基板，其粘附到所述第一基板并且在其上形成有孔; 并且焊球通过形成在第二基板上的孔粘附到电极焊盘。 然后，将第二基板用作阻焊剂。 因此，由于第一基板和第二基板由相同的材料形成，因此可以防止BGA封装在烧制时破裂和不均匀。

公开(公告)号：US20090114434A1

公开(公告)日：2009-05-07

申请号：US12264883

申请日：2008-11-04

Applicant: Min Ji Ko ,  Jong Myeon Lee ,  Eun Tae Park

Inventor： Min Ji Ko ,  Jong Myeon Lee ,  Eun Tae Park

IPC: H05K3/10 ,  H05K1/00

CPC classification number: H05K3/4667 ,  H05K1/0306 ,  H05K3/1291 ,  H05K3/38 ,  H05K3/4611 ,  H05K2201/017 ,  H05K2203/025 ,  H05K2203/1126 ,  H05K2203/1476 ,  H05K2203/308

Abstract: There is provided a method of manufacturing a non-shrinkage ceramic substrate, and a non-shrinkage ceramic substrate using the same. A method of manufacturing a non-shrinkage ceramic substrate by firing a ceramic laminate including an internal electrode circuit pattern according to an aspect of the invention may include: laminating at least one constraining ceramic sheet on each of the upper and lower surfaces of the ceramic laminate to form constraining layers; performing a primary firing process on the ceramic laminate having the constraining layers thereon; polishing the surface of the ceramic laminate from which the constraining layers are removed; forming ceramic paste on the polished surface of the ceramic laminate while exposing connection terminals of the internal electrode circuit pattern to the outside environment through openings in the ceramic paste; forming a surface electrode on the surface of the ceramic paste by patterning so that the surface electrode is electrically connected to the connection terminals; and performing a secondary firing process so that the surface electrode adheres to the ceramic paste.

Abstract translation: 提供了一种制造非收缩陶瓷基板的方法和使用其的非收缩陶瓷基板。 通过烧结根据本发明的一个方面的内部电极电路图案的陶瓷层压体制造非收缩陶瓷基板的方法可以包括：在陶瓷层压体的上表面和下表面的每一个上层叠至少一个约束陶瓷片 形成约束层; 在其上具有约束层的陶瓷层压板上进行初步烧制工艺; 抛光除去约束层的陶瓷层压体的表面; 在陶瓷层压板的抛光表面上形成陶瓷浆料，同时通过陶瓷膏中的开口将内部电极电路图案的连接端子暴露于外部环境; 通过图案化在陶瓷浆料的表面上形成表面电极，使得表面电极电连接到连接端子; 并进行二次烧成工序，使表面电极粘附在陶瓷糊上。

公开(公告)号：US20060000542A1

公开(公告)日：2006-01-05

申请号：US10882745

申请日：2004-06-30

Applicant: Yongki Min ,  Cengiz Palanduz

Inventor： Yongki Min ,  Cengiz Palanduz

IPC: C03B29/00

CPC classification number: H01G4/1227 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/162 ,  H05K2201/017 ,  H05K2201/0355

Abstract: A method including forming a capacitor structure including an electrode material and a ceramic material on the electrode material; and sintering the ceramic material under a condition where a point defect state of the ceramic material defines the ceramic material as insulating without oxidation of the electrode material. A method including depositing a ceramic material on an electrically conductive foil; and sintering the ceramic material in a reducing atmosphere at a temperature that minimizes the mobility of point defects to transition to a level corresponding to a greater conductivity of the ceramic material. An apparatus including a first electrode; a second electrode; and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material includes a thickness less than one micron and a leakage current corresponding to a thermodynamic state wherein a concentration of mobile point defects have been optimized.

Abstract translation: 一种包括在电极材料上形成包括电极材料和陶瓷材料的电容器结构的方法; 并且在陶瓷材料的点缺陷状态将陶瓷材料定义为绝缘而不氧化电极材料的条件下烧结陶瓷材料。 一种方法，包括在导电箔上沉积陶瓷材料; 以及在使缺陷的迁移率最小化以转变到对应于陶瓷材料的更大导电率的水平的温度下，在还原气氛中烧结陶瓷材料。 一种装置，包括：第一电极; 第二电极; 以及设置在所述第一电极和所述第二电极之间的陶瓷材料，其中所述陶瓷材料包括小于1微米的厚度和对应于已经优化了移动点缺陷的浓度的热力学状态的泄漏电流。

公开(公告)号：US20050231926A1

公开(公告)日：2005-10-20

申请号：US11103592

申请日：2005-04-12

Applicant: Hideyuki Ito ,  Kenji Endo

Inventor： Hideyuki Ito ,  Kenji Endo

IPC: H05K1/09 ,  H03H7/42 ,  H05K1/03 ,  H05K3/18 ,  H05K3/20 ,  H05K3/24 ,  H05K3/28 ,  H05K7/06

CPC classification number: H05K3/246 ,  H03H7/422 ,  H05K1/0256 ,  H05K3/207 ,  H05K3/28 ,  H05K2201/017 ,  H05K2201/0347 ,  H05K2201/0769 ,  H05K2203/0113 ,  H05K2203/0315

Abstract: A wiring board includes an insulating inorganic base, a conductor pattern provided on the base and including silver, a nickel oxide layer provided on the conductor pattern and covering the conductor pattern, and an insulating layer provided on the nickel oxide layer. The conductor pattern includes 5 wt % to 12 wt % of phosphorus. This wiring board is prevented from having migration at the conductor pattern, thus being prevented insulation failure at the conductor pattern.

Abstract translation: 布线基板包括绝缘无机基体，设置在基底上的包括银的导体图案，设置在导体图案上并覆盖导体图案的氧化镍层以及设置在氧化镍层上的绝缘层。 导体图案包括5重量％至12重量％的磷。 防止该布线板在导体图案上迁移，从而防止导体图案处的绝缘失效。

公开(公告)号：US20050204864A1

公开(公告)日：2005-09-22

申请号：US10801326

申请日：2004-03-16

Applicant: William Borland ,  Olga Renovales ,  Jerome Smith

Inventor： William Borland ,  Olga Renovales ,  Jerome Smith

IPC: C22C1/05 ,  C22C32/00 ,  H01G4/008 ,  H01G4/12 ,  H05K1/09 ,  H05K1/16

CPC classification number: H01G4/0085 ,  C22C32/0089 ,  H01G4/1227 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/017 ,  H05K2201/0355

Abstract: Conductive powder and paste compositions are formed having desirable electrical and physical properties. The conductive powder and paste compositions may be used in combination with dielectric powder and thick-film paste compositions, which are formed having high dielectric constants, low loss tangents, and other desirable electrical and physical properties, to form capacitors and other fired-on-foil passive circuit components.

Abstract translation: 形成具有所需电学和物理性质的导电粉末和糊剂组合物。 导电粉末和糊剂组合物可与电介质粉末和厚膜糊剂组合物组合使用，其形成具有高介电常数，低损耗切线和其它所需的电学和物理性能，以形成电容器和其它燃烧 - 箔无源电路组件。