公开(公告)号：US20080205013A1

公开(公告)日：2008-08-28

申请号：US12037958

申请日：2008-02-27

Applicant: Yoshikazu OSHIKA ,  Munenori HASHIMOTO ,  Masayuki NAKANO

Inventor： Yoshikazu OSHIKA ,  Munenori HASHIMOTO ,  Masayuki NAKANO

IPC: H05K7/06 ,  H05K3/40 ,  C22C5/02

CPC classification number: H05K3/3463 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1301 ,  H01L2924/157 ,  H01L2924/15787 ,  H05K2201/0269 ,  H05K2203/1105 ,  H05K2203/1157 ,  Y10T29/49149 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A solder layer and an electronic device bonding substrate having high bonding strength of a device and low bonding failure even by a simplified bonding method of a device to a substrate and a method for manufacturing the same are provided.A device bonding substrate 1 including a substrate 2 and a lead free solder layer 5 formed on said substrate has a solder layer 5 consisting of a plurality of layers having mutually different phases, and oxygen concentration on the upper surface of the solder layer is lower than 30 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer 5. Carbon concentration on the upper surface of the solder layer 5 may be lower than 10 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer.

Abstract translation: 提供了一种焊接层和具有高的器件结合强度和低接合故障的电子器件接合衬底，即使通过简化的器件对衬底的接合方法及其制造方法也是如此。 包括形成在所述基板上的基板2和无铅焊料层5的器件接合基板1具有由具有相互不同相的多个层构成的焊料层5，焊料层的上表面的氧浓度低于 在构成焊料层5的上层的金属成分中，最可氧化的金属成分的浓度为30原子％。 焊料层5的上表面上的碳浓度可以低于构成焊料层的上层的金属成分中最可氧化的金属成分的浓度的10原子％。

公开(公告)号：US07390551B2

公开(公告)日：2008-06-24

申请号：US10884722

申请日：2004-07-02

Applicant: Aaron K. Amstutz ,  Thomas J Grabenstetter ,  Randall G. Sommer ,  Christopher J. Stickling

Inventor： Aaron K. Amstutz ,  Thomas J Grabenstetter ,  Randall G. Sommer ,  Christopher J. Stickling

IPC: B32B1/04

CPC classification number: B29C45/14819 ,  B29C43/146 ,  B29C43/18 ,  B29C43/52 ,  B29K2995/0087 ,  B32B7/02 ,  H05K3/284 ,  H05K2201/0269 ,  H05K2203/1316 ,  H05K2203/1322 ,  Y10T428/23 ,  Y10T428/233 ,  Y10T428/239

Abstract: A system and method for encapsulating and protecting a component assembly is disclosed. A barrier system comprising a first layer having a first set of physical properties and a second layer having a second set of physical properties is adapted to protectively surround the component assembly. A continuous transitory material is formed between the first layer and the second layer at associated first and second margin portions such that the first layer and the second layer are not prone to delamination. The physical properties of each layer of the barrier system provide protection to the component assembly from various types of physical and environmental damage.

Abstract translation: 公开了一种用于封装和保护部件组件的系统和方法。 包括具有第一组物理性质的第一层和具有第二组物理性质的第二层的屏障系统适于保护性地围绕该组件组件。 在相关联的第一和第二边缘部分处，在第一层和第二层之间形成连续的短暂材料，使得第一层和第二层不易分层。 每个屏障系统层的物理特性为组件组件提供了对各种物理和环境损害的保护。

公开(公告)号：US20060204733A1

公开(公告)日：2006-09-14

申请号：US11362516

申请日：2006-02-27

Applicant: Makoto Murai ,  Ryosuke Usui

Inventor： Makoto Murai ,  Ryosuke Usui

IPC: B32B3/00

CPC classification number: C23C28/00 ,  C23C28/322 ,  C23C28/345 ,  H01L23/3121 ,  H01L23/3733 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0315 ,  Y10T428/24331 ,  Y10T428/24917 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: The present invention provides a circuit device capable of controlling deformation of a circuit device while preventing an insulating layer from peeling from a substrate. The circuit device includes a substrate, an insulating layer formed on the substrate, a filler filled into the insulating layer, a conductive layer formed on the insulating layer, and a circuit element formed on the conductive layer, wherein an average particle diameter of the filler filled into the insulating layer is controlled so that a Young's modulus of a part of the insulating layer on a substrate side can be smaller than a Young's modulus of a part of the insulating layer on an opposite side relative to the substrate side.

公开(公告)号：US20060158497A1

公开(公告)日：2006-07-20

申请号：US11331237

申请日：2006-01-13

Applicant: Karel Vanheusden ,  James Howarth ,  Chuck Edwards

Inventor： Karel Vanheusden ,  James Howarth ,  Chuck Edwards

IPC: G01D11/00

CPC classification number: H05K3/125 ,  H01L51/0022 ,  H05K1/024 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/323 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0269 ,  H05K2203/013 ,  H05K2203/1476

Abstract: A process for fabricating an electrical component having at least one anisotropic electrical quality is provided. The process includes the step of ink-jet printing a plurality of dots of each of at least two electronic inks in a predetermined pattern such that the anisotropic electrical quality is manifested. The ink-jet printing step may further include the steps of: selecting a first electronic ink having a known first electrical characteristic; selecting a second electronic ink having a known second electrical characteristic; determining a positional layout for each of a plurality of dots for each of the first and second electronic inks such that the determined positional layout provides a response of the electrical component in accordance with the anisotropic electrical quality; and printing each of the plurality of dots of each of the first and second electronic inks onto a substrate according to the determined positional layout.

Abstract translation: 提供一种用于制造具有至少一种各向异性电气质量的电气部件的工艺。 该方法包括以预定图案喷墨打印至少两种电子墨水中的每一个的多个点的步骤，使得各向异性电气质量得以体现。 喷墨打印步骤还可以包括以下步骤：选择具有已知的第一电特性的第一电子墨水; 选择具有已知第二电特性的第二电子墨水; 确定所述第一和第二电子墨水中的每一个的多个点中的每一个的位置布局，使得所确定的位置布局根据所述各向异性电气质量提供所述电气部件的响应; 并且根据确定的位置布局将每个第一和第二电子墨水的多个点中的每一个打印到基底上。

公开(公告)号：US5093186A

公开(公告)日：1992-03-03

申请号：US584641

申请日：1990-09-19

Applicant: Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Sumihito Tominaga ,  Rokuro Kanbe

Inventor： Yukihiro Kimura ,  Nobuhiko Miyawaki ,  Sumihito Tominaga ,  Rokuro Kanbe

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/40

CPC classification number: H05K1/0271 ,  H05K3/4061 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A multilayer ceramic wiring board including a ceramic board having a plurality of through-holes and formed by laminating three or more green sheets of a ceramic material and burning a laminate of the green sheets, and a plurality of conductors provided in the through-holes. Each of the conductors is formed of a ceramic material and a conductive material in combination. The ceramic board is composed of a pair of upper and lower layer portions each having at least an outermost surface layer and an inner layer portion disposed between the upper and lower portions. The conductors are composed of an outer conductor portion formed in the upper and lower layer portions and an inner conductor portion formed in the inner layer portion. The outer conductor portion has a content ratio of the ceramic material higher than that of the inner conductor portion. Accordingly, the generation of cracks in the outer conductor portion disposed at the upper and lower layer portions of the ceramic board can be prevented, and an electric resistance can be reduced.

Abstract translation: 一种多层陶瓷布线板，包括具有多个通孔的陶瓷板，并且通过层叠三种或更多种陶瓷材料的生片并烧制生片的层压体，以及设置在通孔中的多个导体。 每个导体由陶瓷材料和导电材料组合形成。 陶瓷板由一对上下层部分组成，每一层至少具有最外表面层和设置在上部和下部之间的内层部分。 导体由形成在上层部和下层部中的外部导体部和形成在内层部的内部导体部构成。 外导体部分的陶瓷材料的含量比高于内导体部分的含量比。 因此，可以防止在布置在陶瓷板的上层和下层部分的外导体部分中产生裂纹，并且可以降低电阻。

公开(公告)号：US4784893A

公开(公告)日：1988-11-15

申请号：US14742

申请日：1987-02-13

Applicant: Yoshio Nishimoto ,  Kiyoshi Hani ,  Shohei Etoh

Inventor： Yoshio Nishimoto ,  Kiyoshi Hani ,  Shohei Etoh

IPC: B32B7/02 ,  H05K1/03 ,  H05K1/05 ,  B32B3/00 ,  D21D3/00

CPC classification number: H05K1/0366 ,  B32B7/02 ,  H05K1/0386 ,  H05K2201/0209 ,  H05K2201/0251 ,  H05K2201/0269 ,  H05K2201/0278 ,  H05K2201/0293 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24934 ,  Y10T428/31993 ,  Y10T442/616 ,  Y10T442/656

Abstract: A heat conductive circuit board includes an insulating layer provided on a metal substrate, and an electrically conductive metal foil formed on the insulating layer, and the insulating layer is formed by impregnating an alumina paper with organic polymer. The alumina paper is made by subjecting a material containing alumina fiber as the principal components to a paper-making process. The insulating layer has excellent properties of heat transfer not only in the thickness direction but also in the surface direction, and thus, the heat conductive circuit board is excellent in heat dissipation properties.

Abstract translation: 导热电路板包括设置在金属基板上的绝缘层和形成在绝缘层上的导电金属箔，并且通过用有机聚合物浸渍氧化铝纸形成绝缘层。 氧化铝纸通过将含有氧化铝纤维的材料作为主要成分进行制造。 绝缘层不仅在厚度方向上而且在表面方向上具有优异的热传递性，因此导热电路板的散热特性优异。

公开(公告)号：USRE49929E1

公开(公告)日：2024-04-16

申请号：US17528405

申请日：2021-11-17

Applicant: Sumitomo Electric Industries, Ltd. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Shingo Kaimori ,  Masaaki Yamauchi ,  Kentaro Okamoto ,  Satoshi Kiya ,  Kazuo Murata

IPC: H05K1/03 ,  B32B15/08 ,  B32B15/082 ,  B32B15/20 ,  B32B27/20 ,  B32B27/30 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00 ,  H05K3/38

CPC classification number: H05K1/0373 ,  B32B15/08 ,  B32B15/082 ,  B32B15/20 ,  B32B27/20 ,  B32B27/30 ,  H05K1/0271 ,  H05K1/03 ,  H05K1/034 ,  H05K1/09 ,  H05K3/0055 ,  H05K3/381 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/029 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2203/1194

Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 μm, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.

公开(公告)号：US20170303396A1

公开(公告)日：2017-10-19

申请号：US15487560

申请日：2017-04-14

Applicant: IBIDEN CO., LTD.

Inventor： Hiroyuki Nishioka ,  Shinsuke Ishikawa

IPC: H05K1/11 ,  H05K3/28 ,  H05K3/00 ,  H05K1/03 ,  G03F7/40 ,  G03F7/038 ,  G03F7/031 ,  G03F7/16 ,  G03F7/09 ,  G03F7/039 ,  G03F7/20 ,  G03F7/32

CPC classification number: H05K1/113 ,  G03F7/028 ,  G03F7/031 ,  G03F7/038 ,  G03F7/039 ,  G03F7/094 ,  G03F7/095 ,  G03F7/16 ,  G03F7/168 ,  G03F7/2004 ,  G03F7/32 ,  G03F7/40 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/112 ,  H05K3/0055 ,  H05K3/282 ,  H05K3/287 ,  H05K3/3452 ,  H05K2201/0195 ,  H05K2201/0269 ,  H05K2203/0776

Abstract: A printed wiring board includes a laminated base material including an insulating layer and a conductor layer formed on the insulating layer, and a solder resist layer laminated on the laminated material and including photosensitive resin. The resist layer has surface portion and portion in contact with the laminated material, the conductor layer has pattern including conductor pads in contact with the resist layer such that the pads are positioned in openings in the resist layer, and the resist layer satisfies a first condition that a chemical species derived from a photopolymerization initiator has concentration higher in the portion in contact with the laminated material than concentration in the surface portion and/or a second condition that the chemical species derived from the initiator in the portion in contact with the laminated material has photopolymerization initiating ability higher than a chemical species derived from a photopolymerization initiator in the surface portion.

公开(公告)号：US20170207190A1

公开(公告)日：2017-07-20

申请号：US15324759

申请日：2015-07-22

Applicant: DEXERIALS CORPORATION

Inventor： Reiji TSUKAO

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/73 ,  G02F1/13458 ,  G02F2202/28 ,  H01L22/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16012 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29357 ,  H01L2224/29371 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2924/1426 ,  H01R4/04 ,  H01R12/7076 ,  H01R13/2414 ,  H05K1/111 ,  H05K3/323 ,  H05K2201/0269 ,  H05K2201/09409 ,  H01L2924/00

Abstract: A connection body includes a circuit board terminals arranged into terminal rows, the terminals rows being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the terminals are arranged, and an electronic component including bumps arranged into bump rows corresponding to the terminal rows, the bumps being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the bumps are arranged. The electronic component is connected upon the circuit board interposed by an anisotropic conductive adhesive including electrically conductive particles arranged therein. A distance between mutually opposing terminals of the terminals and bumps of the bumps arranged toward the outer sides of the circuit board and the electronic component is greater than a distance between mutually opposing terminals of the terminals and bumps of the bumps arranged toward their inner sides.

公开(公告)号：US09578738B2

公开(公告)日：2017-02-21

申请号：US14646065

申请日：2013-11-13

Applicant: KYOCERA Corporation

Inventor： Takeshi Matsui ,  Katsura Hayashi

IPC: H05K1/03 ,  H05K1/02 ,  H05K3/46 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/0373 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2201/09036

Abstract: According to an aspect of the invention, a wiring board includes an inorganic insulating layer and a conductive layer disposed on part of one main surface of the inorganic insulating layer. The part of the one main surface of the inorganic insulating layer includes a plurality of first recessed portions each of which has at least partially circular shape in a plan view. Part of the conductive layer enters into the plurality of first recessed portions. According to the aspect of the invention, it is possible to obtain a wiring board capable of reducing disconnection of the conductive layer and therefore having superior electrical reliability.

Abstract translation: 根据本发明的一个方面，布线板包括无机绝缘层和设置在无机绝缘层的一个主表面的一部分上的导电层。 无机绝缘层的一个主表面的一部分包括在平面图中至少部分为圆形的多个第一凹部。 导电层的一部分进入多个第一凹部。 根据本发明的一个方面，可以获得能够减少导电层的断开并因此具有优异的电可靠性的布线基板。