公开(公告)号：US07528479B2

公开(公告)日：2009-05-05

申请号：US11516005

申请日：2006-09-05

Applicant: Yasuhisa Yamanaka

Inventor： Yasuhisa Yamanaka

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H05K1/0216 ,  H05K1/0218 ,  H05K2201/0723 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/09972

Abstract: Mounting components such as LSIs, which emit noise to the outside and are subjected to the influence of external noise, on the top-most layer and the bottom-most layer respectively, a co-existing layer of the ground region and the power source region has been employed, where a ground region has been provided respectively to the range corresponding to the position the LSIs on the next layer below the top-most layer and the next layer above the bottom-most layer. Accordingly, the number of layers to be laminated to form the multilayer substrate has been reduced, because it is no longer required, unlike the related art, to provide a ground layer where the ground pattern is formed substantially over the entire surface of layer respectively to the next layer below the top-most layer having mounted a LSI thereon and of the next layer above the bottom-most layer having mounting a LSI thereon.

Abstract translation: 分别在最上层和最底层上分别向外部发出噪声并受到外部噪声的影响的诸如LSI的安装部件，接地区域和电源区域的共存层 已经使用了地面区域分别设置在与最上层下面的下一层的LSI的位置相对应的范围和最底层以上的下一层的范围内。 因此，与现有技术不同，由于不再需要层叠以形成多层基板的层的数量，因此提供接地层，其基本上在层的整个表面上分别形成接地图案， 在其上安装有LSI的最上层的下一层和在其上安装有LSI的最底层之上的下一层。

公开(公告)号：US07405947B1

公开(公告)日：2008-07-29

申请号：US11809595

申请日：2007-06-01

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/16

CPC classification number: H05K1/0237 ,  H05K1/0219 ,  H05K1/0225 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09663

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract translation: 对于电气背板等，公开了一种用于改进高速信号通过嵌入式电源平面中的间隙的传播的电力平面适配。 在示例性实施例中，电力平面在高速连接器区域中被分段，使得形成电力平面的金属层的一部分保持在高速连接器区域中，但是与电力输送部分 电力飞机 隔离部分连接到数字地，并且在其中形成间隙，其中高速信令通孔将通过该区域。 在一些实施例中，各种可获得的优点包括更好的可制造性，更好地匹配和控制高速信号通孔阻抗以及改进的噪声隔离。 描述和要求保护其他实施例。

公开(公告)号：US20080165514A1

公开(公告)日：2008-07-10

申请号：US11762365

申请日：2007-06-13

Applicant: Yong-won HWANG

Inventor： Yong-won HWANG

IPC: H05K3/00 ,  H05K7/02

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09345 ,  Y10T29/4913

Abstract: A printed circuit board (PCB) having a multi-layered structure for improving shielding against electromagnetic interference, the PCB including one or more signal layers and an outer grounding layer located on an outermost surface of the PCB. Accordingly, the radiation of electromagnetic waves to the outside from the outer grounding layer is prevented.

Abstract translation: 一种具有用于改善屏蔽电磁干扰的多层结构的印刷电路板（PCB），该PCB包括一个或多个信号层和位于该PCB的最外表面上的外部接地层。 因此，防止了从外部接地层向外部的电磁波的辐射。

公开(公告)号：US07385792B2

公开(公告)日：2008-06-10

申请号：US10928172

申请日：2004-08-30

Applicant: Mitsuhiro Kanayama ,  Toru Itabashi

Inventor： Mitsuhiro Kanayama ,  Toru Itabashi

IPC: H02H7/00

CPC classification number: H02M3/00 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10166

Abstract: An electronic control apparatus includes an exclusive power source line for a charge pump circuit which is discriminated from a common power source line. The exclusive power source line is connected to the common power source wiring via a via-hole va having an impedance larger than that of the exclusive source line. Similarly, the electronic control apparatus includes an exclusive ground line for the charge pump circuit which is discriminated from a common ground line. The exclusive ground line is connected to the common ground via an additional via-hole vb. Furthermore, a noise-suppressing capacitor C is connected between the exclusive power source and around lines.

Abstract translation: 电子控制装置包括用于与公共电源线区别的电荷泵电路的专用电源线。 专用电源线通过具有比排他源线的阻抗大的阻抗的通孔va连接到公共电源布线。 类似地，电子控制装置包括用于与公共接地线区别的电荷泵电路的专用接地线。 专用地线通过附加的通孔vb连接到公共地。 此外，噪声抑制电容器C连接在专用电源和绕线之间。

公开(公告)号：US07157646B2

公开(公告)日：2007-01-02

申请号：US10882167

申请日：2004-07-02

Applicant: John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

Inventor： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC: H05K1/11

CPC classification number: H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

Abstract: A circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.

Abstract translation: 电路化基板，其包括多个邻接的开放段，其在导电层内限定面对的边缘部分，以隔离导电层的分离部分，使得该层可用于不同的功能，例如功率和接地元件内部的功能和接地元件 包括基板作为其一部分的产品（例如，电气组件）。 还提供了制造衬底的方法，利用衬底的电组件，还利用衬底的多层电路化组件和诸如主机的信息处理系统。

公开(公告)号：US07012810B2

公开(公告)日：2006-03-14

申请号：US10109555

申请日：2002-03-27

Applicant: Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

Inventor： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

IPC: H01R9/00

CPC classification number: H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H02M7/003 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K7/1432 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49009 ,  Y10T29/49117 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

公开(公告)号：US20030141585A1

公开(公告)日：2003-07-31

申请号：US10064426

申请日：2002-07-12

Inventor： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC: H01L021/44

CPC classification number: H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

Abstract translation: 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以由 相同的控制芯片。

公开(公告)号：US20030053302A1

公开(公告)日：2003-03-20

申请号：US09955230

申请日：2001-09-18

Inventor： Christopher J. Kelly ,  Jeffrey L. Krieger ,  Raymond P. Askew

IPC: H05K007/06

CPC classification number: H05K1/0233 ,  H05K1/0237 ,  H05K1/0243 ,  H05K3/4644 ,  H05K2201/086 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

Abstract: A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.

Abstract translation: 印刷电路板包括信号层和电源电压平面层。 信号层包括用于传送与调节电源电压无关的信号的迹线。 电源电压平面嵌入在信号层中，为安装到印刷电路板的部件的多个电源电压引脚供电。 印刷电路板还可以包括用于传送电源电压的电源电压平面层。 接地平面可以嵌入在电源电压平面层中，以提供与组件的多个引脚的接地连接。

公开(公告)号：US20030042044A1

公开(公告)日：2003-03-06

申请号：US09945394

申请日：2001-08-30

Applicant: Micron Technology, Inc.

Inventor： Steve Van Kirk

IPC: H05K007/06

CPC classification number: H05K1/162 ,  H05K2201/09236 ,  H05K2201/09345

Abstract: A circuit board is provided. The circuit board includes two conductive layers, either horizontally-opposed, or vertically-overlapping, formed around a dielectric layer. Mutually-engaging interstices or tongues and grooves are formed in each conductive layer, with the dielectric disposed between them. The interstices (or tongues and grooves) are typically formed in a complementary shape, but this is not necessary. Any number of interstices and/or tongues and grooves may be formed into the conductive layers. The amount of engagement between the interstices, or the amount each conductive layer overlaps the other along its width, may be selected to provide a predetermined amount of capacitance between the conductive layers. The dielectric layer dielectric constant may also be selected in order to adjust the capacitance formed between the conductive layers. Other embodiments of the invention include electronic circuits and methods for constructing the disclosed circuit boards and related electronic circuits.

Abstract translation: 提供电路板。 电路板包括围绕电介质层形成的两个导电层，水平相对或垂直重叠。 在每个导电层中形成相互接合的间隙或舌状物和沟槽，其中电介质设置在它们之间。 间隙（或舌头和凹槽）通常形成为互补形状，但这不是必需的。 可以在导电层中形成任何数量的间隙和/或舌和凹槽。 可以选择间隙之间的接合量或每个导电层沿其宽度与另一导电层重叠的量，以在导电层之间提供预定量的电容。 还可以选择介电层介电常数，以便调节在导电层之间形成的电容。 本发明的其他实施例包括用于构建所公开的电路板和相关电子电路的电子电路和方法。

公开(公告)号：US20020126465A1

公开(公告)日：2002-09-12

申请号：US09957001

申请日：2001-09-20

Inventor： Douglas Maly ,  Sayeed Ahmed ,  Scott Parkhill ,  Fred Flett

IPC: H05K009/00

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A high frequency, low impedance network is integrated into the substrate level of a power module for the reduction of electromagnetic interference (nullEMInull). In one embodiment, capacitance is electrically connected to at least one of the positive conducting layer in a substrate or the negative conducting layer in a substrate and a ground. Integrating a capacitive network of low stray inductance in a substrate of a power module allows relatively small, inexpensive capacitors to be used.

Abstract translation: 高频，低阻抗网络被集成在功率模块的基板级中，以减少电磁干扰（“EMI”）。 在一个实施例中，电容电连接到衬底中的正导电层中的至少一个或衬底中的负导电层和接地。 将低杂散电感的电容网络集成在功率模块的基板中允许使用相对较小的便宜的电容器。