公开(公告)号：US20030218243A1

公开(公告)日：2003-11-27

申请号：US10063880

申请日：2002-05-21

Inventor： Kuo-Ming Chen

IPC: H01L023/48

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/3511 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00

Abstract: Solder pads for improving reliability of a semiconductor package are provided. The package includes a substrate and/or a chip. The solder pad includes a plurality of first solder pads located on a surface of the substrate and/or the chip, and at least a second solder pad located on a predetermined region of the surface of the substrate and/or the chip. Each of the first solder pads has a first diameter. The second solder pad has a second diameter greater than the first diameter so as to sustain a stronger thermal stress on the substrate and/or the chip.

Abstract translation: 提供了用于提高半导体封装的可靠性的焊盘。 封装包括衬底和/或芯片。 焊盘包括位于衬底和/或芯片的表面上的多个第一焊盘，以及位于衬底表面和/或芯片的预定区域上的至少第二焊盘。 每个第一焊盘具有第一直径。 第二焊盘具有大于第一直径的第二直径，以便在衬底和/或芯片上维持更强的热应力。

公开(公告)号：US20030198031A1

公开(公告)日：2003-10-23

申请号：US10125287

申请日：2002-04-18

Inventor： Melvin Peterson

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/10

CPC classification number: H05K1/112 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A multilayered substrate includes a plurality of connection point groups, each including connection points. At least two inside conductors are each electrically coupled to inside connection points in at least two connection point groups, wherein each of the inside conductors is substantially equal in length between the inside connection points of adjacent connection point groups which is defined as a inside conductor length. At least two outside conductors are each electrically coupled to outside connection points in at least two connection point groups, wherein each of the outside conductors is substantially equal in length between the outside connection points of the adjacent connection point groups which is defined as an outside conductor length. The inside conductor length is shorter than the outside conductor length.

Abstract translation: 多层基板包括多个连接点组，每个连接点组包括连接点。 至少两个内部导体每个电连接到至少两个连接点组中的内部连接点，其中每个内部导体在相邻连接点组的内部连接点之间的长度上基本上相等，所述连接点组被定义为内部导体长度 。 至少两个外部导体分别在至少两个连接点组中电耦合到外部连接点，其中每个外部导体在被定义为外部导体的相邻连接点组的外部连接点之间的长度上基本相等 长度。 内部导体长度短于外部导体长度。

公开(公告)号：US20030156391A1

公开(公告)日：2003-08-21

申请号：US10311993

申请日：2003-02-11

Inventor： Mitsushisa Nakai ,  Keiichi Kuriyama ,  Akihiro Kyogoku ,  Yoshinao Nakamoto ,  Koji Taniguchi ,  Hiroaki Higashi

IPC: H05K001/00 ,  H05K001/18 ,  H05K007/02 ,  H05K007/06 ,  H05K007/08

CPC classification number: H05K3/3468 ,  H05K1/111 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09418 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

Abstract: A circuit board comprising a first solder leading land 13a disposed next to a mounting land located rearmost in a direction the circuit board moving during flow soldering of an electronic component, and a second solder leading land 13b disposed behind the first solder leading land 13a against the direction. The present invention provides a circuit board which can effectively prevent solder bridges caused by excessive solder accumulated around leads and lands located in the rearmost position while the electronic component is flow soldered at narrow pitches as is represented by a case with QFPIC. The circuit board of the present invention is suitable for use of lead-free solder, thus contributes to an environment protection.

Abstract translation: 一种电路板，包括：第一焊料引导焊盘13a，设置在靠近电子部件流动焊接期间移动的电路板方向最后方的位置最靠前的安装焊盘;以及设置在第一焊料引导焊盘13a后面的第二焊接引导焊盘13b， 方向。 本发明提供了一种电路板，其可以有效地防止由位于最后面位置的引线和焊盘周围累积的过量焊料引起的焊料桥，同时电子部件以窄间距流动焊接，如用QFPIC的情况所示。 本发明的电路板适用于无铅焊料，有助于环境保护。

公开(公告)号：US06594811B2

公开(公告)日：2003-07-15

申请号：US10014972

申请日：2001-10-26

Applicant: Walter M. Katz

Inventor： Walter M. Katz

IPC: G06F1650

CPC classification number: H01L23/49838 ,  G06F2217/40 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/09701 ,  H01L2924/3025 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/10734

Abstract: Patterns for a routable interface of the signal lines of a integrated circuit device include several groups of terminals distributed about the pattern center, each group clustered along a corresponding curvilinear reference segment extending outward from the pattern center to its perimeter. Routability zones are created between each successive pair of groups. For higher terminal density, in at least one of the terminal groups of the pattern, either the offset of the terminals from the reference line segment is not uniform, or the distance of the terminals from the pattern center does not increase uniformly. A portion, preferably at least about 50% of the terminals in a group of the pattern are not collinear with, but offset from, the reference segment. A portion, preferably at least about 90% of the terminals in a given terminal group are each closer to the reference line segment of that terminal group than they are to the reference segment of another terminal group. The patterns of this invention can be employed on IC chips, IC package layers and PCB layers for patterning of terminals, pins, via, pads and another connector devices useful in IC devices.

公开(公告)号：US06487082B1

公开(公告)日：2002-11-26

申请号：US09620059

申请日：2000-07-20

Applicant: Thomas Alex Crapisi ,  Jeffrey S. Conger ,  Stephen Cermak, III ,  Stephen A. Bowen ,  Rodney Ruesch ,  David Paul Gruber ,  Bonnie Kay Dobbs

Inventor： Thomas Alex Crapisi ,  Jeffrey S. Conger ,  Stephen Cermak, III ,  Stephen A. Bowen ,  Rodney Ruesch ,  David Paul Gruber ,  Bonnie Kay Dobbs

IPC: H05K710

CPC classification number: H05K1/181 ,  H05K1/023 ,  H05K1/18 ,  H05K2201/09418 ,  H05K2201/10022 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A printed circuit board apparatus, configurations and methods are presented which provide for close spacing between the HUB and multiple processors as well as a common configuration for two or four processor boards. A printed circuit board is provided with conductive apertures and portions corresponding to an efficient Packaging allowing for the attachment of the processor-chip on one side of the printed circuit board, and the HUB and other supporting electronic components on the other side of the printed circuit board. This configuration allows for the close spacing of the electrical conductors of the HUB and the processors without the limitations imposed by the physical dimensions of the respective hardware. Additionally, a symmetric packaging of the conductive apertures and portions about a centerline of the printed circuit board allows for a simple design modification to allow for a two two-processor board to be manufactured from a similarly configured four-processor board.

Abstract translation: 提出了一种印刷电路板装置，配置和方法，其提供了HUB和多个处理器之间的紧密间隔以及用于两个或四个处理器板的通用配置。 印刷电路板设置有导电孔和对应于有效包装的部分，其允许在印刷电路板的一侧上附接处理器芯片，并且在印刷电路的另一侧上的HUB和其他支撑电子部件 板。 该配置允许HUB和处理器的电导体的紧密间隔，而不受相应硬件的物理尺寸施加的限制。 此外，导电孔和印刷电路板的中心线周围的部分的对称封装允许简单的设计修改，以允许由类似配置的四处理器板制造两个两处理器板。

公开(公告)号：US20020081768A1

公开(公告)日：2002-06-27

申请号：US09992315

申请日：2001-11-19

Inventor： Koji Yoshida

IPC: H01L021/50 ,  H01L021/44 ,  H01L021/48

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/45144 ,  H01L2224/81206 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0665 ,  H05K3/328 ,  H05K2201/09418 ,  H05K2201/10674 ,  H05K2203/0285 ,  Y02P70/611 ,  H01L2924/00

Abstract: A semiconductor device includes a wiring pattern formed on a board, and a semiconductor chip bonded to the wiring pattern by ultrasonic welding. The wiring pattern is formed such that when the semiconductor chip is disposed on the wiring pattern, a range shared between the wiring pattern and positional variation regions of portions to be bonded of the semiconductor chip accompanied by the ultrasonic welding becomes as wide as possible. Such a semiconductor device makes it possible to ensure a sufficient positional deviation range of a wiring pattern with respect to a positional deviation in each bump type electrode, and hence to cope with a multi-pin structure for flip-chip mounting and to improve both an initial bonding characteristic and a mounting reliability.

Abstract translation: 半导体器件包括形成在基板上的布线图案和通过超声波焊接接合到布线图案的半导体芯片。 布线图形形成为使得当半导体芯片布置在布线图案上时，伴随着超声波焊接的半导体芯片的布线图案和待粘接部分的位置变化区域之间共有的范围变得越来越宽。 这样的半导体器件使得可以确保布线图案相对于每个凸块型电极中的位置偏差的足够的位置偏移范围，因此可以应对用于倒装芯片安装的多引脚结构，并且改善两者 初始粘合特性和安装可靠性。

公开(公告)号：US6143992A

公开(公告)日：2000-11-07

申请号：US160105

申请日：1998-09-24

Applicant: Shingo Sato ,  Seigo Matsuzono ,  Kenshi Nakamura

Inventor： Shingo Sato ,  Seigo Matsuzono ,  Kenshi Nakamura

IPC: H01L21/60 ,  H01L23/12 ,  H05K1/11 ,  H05K3/34 ,  H01R12/04

CPC classification number: H05K1/111 ,  H05K3/3436 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/52 ,  H01R12/57 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2201/10734 ,  H05K2203/0465 ,  H05K3/3452 ,  Y02P70/611 ,  Y02P70/613

Abstract: A circuit board of the invention comprises: an insulating base, which has a semiconductor element mounting portion on an top or bottom side thereof, and on which wiring patterns led out of the semiconductor element mounting portion are installed; and a plurality of substantially circular terminal pads, which are formed on the bottom side of the insulating base, which are connected to the wiring patterns, and to which solder terminals will be joined, wherein each of the terminal pads is provided with a solder lead portion which projects from a center side toward a perimeter side of the insulating base in a diametrical direction of the terminal pad. A part of the solder terminal is pulled out at the solder lead portion, whereby it is possible to prevent a fatigue failure of a joint of the terminal pad and the solder terminal due to a concentration of thermal stress, to electrically connect the solder terminal to the terminal pad in a stable manner for a long time period.

Abstract translation: 本发明的电路板包括：绝缘基座，其顶部或底部具有半导体元件安装部分，并且其上布置有从半导体元件安装部分引出的布线图案; 以及多个基本上圆形的端子焊盘，其形成在绝缘基底的底侧上，其连接到布线图案，并且焊接端子将被接合，其中每个端子焊盘设置有焊料引线 该部分在端子垫的直径方向上从绝缘基体的中心侧朝向周边侧突出。 焊锡端子的一部分在焊锡引线部分被拉出，由此可以防止由于热应力集中而导致端子焊盘和焊接端子的接头的疲劳破坏，从而将焊接端子电连接到 终端板以稳定的方式长时间。

公开(公告)号：US5775568A

公开(公告)日：1998-07-07

申请号：US686781

申请日：1996-07-26

Applicant: Jess Asla ,  Roy Lange ,  Ron Despain

Inventor： Jess Asla ,  Roy Lange ,  Ron Despain

IPC: B23K3/06 ,  B23K3/08 ,  H05K3/34

CPC classification number: B23K3/08 ,  B23K3/0676 ,  H05K3/3468 ,  B23K2201/42 ,  H05K2201/09418

Abstract: A method for wave soldering comprises the steps of providing a circuit board having a plurality of electronic components thereon and providing a pallet comprising a frame, first and second parallel rails attached to the frame, and third and fourth rails for receiving the circuit board. The third and fourth rails are attached to the first and second rails and the third and fourth rails form an angle of between about 30.degree. and 60.degree. with the first and second rails. Next, a solder wave is provided which generally flows in a first direction. Finally, the pallet is moved in a second direction generally perpendicular with the first direction across the solder wave. The components are therefore positioned at an angle with respect to the solder wave and solder-related electrical defects are reduced.

Abstract translation: 一种用于波峰焊的方法包括以下步骤：在其上提供具有多个电子部件的电路板，并提供包括框架的托盘，附接到框架的第一和第二平行导轨以及用于接收电路板的第三和第四导轨。 第三和第四轨道附接到第一和第二轨道，并且第三和第四轨道与第一和第二轨道形成在约30度和60度之间的角度。 接下来，提供通常沿第一方向流动的焊波。 最后，托盘在大致垂直于焊料波的第一方向的第二方向移动。 因此，这些部件相对于焊料波形成一角度，并减少焊料相关的电气缺陷。

公开(公告)号：US5605223A

公开(公告)日：1997-02-25

申请号：US500961

申请日：1995-08-02

Applicant: Klaus Gutmann ,  Hans-Werner Luckehe

Inventor： Klaus Gutmann ,  Hans-Werner Luckehe

IPC: H01H13/70 ,  H01H13/785 ,  H05K1/11 ,  H05K3/24 ,  H01H1/06

CPC classification number: H01H13/785 ,  H01H13/7006 ,  H05K1/11 ,  H01H2201/026 ,  H01H2201/03 ,  H01H2203/038 ,  H01H2203/054 ,  H05K2201/0323 ,  H05K2201/09418 ,  H05K2201/0979 ,  H05K2201/10053 ,  H05K3/245

Abstract: In order to produce keyboards, two pairs of diagonally connected squares with rounded corners are used as fixed contacts. A direct diagonal connection electrically connects two non-adjacent squares. The squares are conductive lacquer (carbon lacquer) and cover copper pads on a printed circuit board.

Abstract translation: PCT No.PCT / DE93 / 01197 Sec。 371日期：1995年8月2日 102（e）日期1995年8月2日PCT 1993年11月15日PCT公布。 第WO94 / 17541号公报 日期1994年8月4日为了生产键盘，使用两对带有圆角的对角线连接的正方形作为固定触点。 直接对角连接电连接两个不相邻的正方形。 正方形是导电漆（碳漆），并覆盖印刷电路板上的铜焊盘。

公开(公告)号：US5540376A

公开(公告)日：1996-07-30

申请号：US324087

申请日：1994-10-14

Applicant: Jess Asla ,  Roy Lange ,  Ron Despain

Inventor： Jess Asla ,  Roy Lange ,  Ron Despain

IPC: B23K3/06 ,  B23K3/08 ,  H05K3/34

CPC classification number: B23K3/08 ,  B23K3/0676 ,  H05K3/3468 ,  B23K2201/42 ,  H05K2201/09418

Abstract: A pallet for holding a printed circuit board comprises first and second parallel rails and third and fourth parallel rails. The third and fourth rails each have first and second ends and form an angle of between about 30.degree. and 60.degree. with the first and second rails. The first and second ends of the third and fourth rails are connected to one of the first and second rails. The pallet further comprises an attachment for securing the printed circuit board to the third and fourth rails. The angled pallet has advantages over conventional pallets as shorts and shadowing are reduced.

Abstract translation: 用于保持印刷电路板的托盘包括第一和第二平行导轨以及第三和第四平行导轨。 第三和第四导轨各自具有第一和第二端，并且与第一和第二导轨形成在约30度和60度之间的角度。 第三和第四导轨的第一和第二端连接到第一和第二导轨之一。 托盘还包括用于将印刷电路板固定到第三和第四轨道的附件。 倾斜的托盘具有优于传统托盘的优点，因为短裤和阴影减少。