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公开(公告)号:US09871013B2
公开(公告)日:2018-01-16
申请号:US14584748
申请日:2014-12-29
Inventor: Pei-Chun Tsai , Yu-Feng Chen , Tin-Hao Kuo , Chen-Shien Chen , Yu-Chih Huang , Sheng-Yu Wu
CPC classification number: H01L24/17 , H01L23/147 , H01L23/49822 , H01L23/49827 , H01L2224/0401 , H01L2224/16057 , H01L2224/16113 , H01L2224/16227 , H01L2224/16238 , H01L2924/15311 , H01L2924/15313 , H05K1/111 , H05K2201/0969 , H05K2201/10378 , H05K2201/10674 , Y02P70/611
Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.
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公开(公告)号:US20180013219A1
公开(公告)日:2018-01-11
申请号:US15545698
申请日:2015-03-20
Applicant: Unid Co., Ltd.
Inventor: Chong Kwang YOON , Young Soo KIM , Yeong Uk SEO , Yeong Joo MOON
CPC classification number: H01R12/73 , H01R12/58 , H01R13/113 , H01R13/24 , H05K1/144 , H05K3/325 , H05K3/3436 , H05K2201/10189 , H05K2201/1031 , H05K2201/10325 , H05K2201/10378 , H05K2201/10962 , Y02P70/611
Abstract: Provided is a matable electrical connection structure including a female connection member and a male connection member respectively including a plurality of first connection portions and a plurality of second connection portions, and a plurality of matable connection portions configured to detachably couple the female connection member and the male connection member, and respectively and electrically connect the plurality of first connection portions to the plurality of second connection portions, and the matable connection portions include inner conductive materials respectively and electrically connected to the plurality of first connection portions and provided on inner walls of a plurality of insertion holes formed in the female connection member, columns respectively and electrically connected to the plurality of second connection portions and configured to protrude from the male connection member to be inserted into the insertion hole, and elastic fins configured to extend outside the column to elastically contact the inner conductive material, and at least one of the female connection member and the male connection member is divided into a plurality of areas, and the plurality of matable connection portions are disposed to form a group in each of the areas.
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公开(公告)号:US20180012879A1
公开(公告)日:2018-01-11
申请号:US15205702
申请日:2016-07-08
Applicant: Cisco Technology, Inc.
Inventor: Paul L. Mantiply , Straty Argyrakis
IPC: H01L25/18 , H05K1/18 , H01L23/538 , H05K3/34 , H01L25/00 , H01L23/367 , H02M3/158 , H05K1/02 , H05K1/11 , H01L23/498 , H01L25/16 , H01L23/00
CPC classification number: H01L25/18 , H01L23/3675 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/17 , H01L25/16 , H01L25/50 , H01L2924/10253 , H01L2924/10329 , H01L2924/1033 , H01L2924/1306 , H01L2924/1426 , H01L2924/1427 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19102 , H02M3/158 , H05K1/0204 , H05K1/0262 , H05K1/0298 , H05K1/115 , H05K1/181 , H05K1/185 , H05K3/341 , H05K3/3436 , H05K2201/10015 , H05K2201/1003 , H05K2201/10166 , H05K2201/10378 , H05K2201/10545 , H05K2201/10734
Abstract: Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a substrate, an ASIC, and a voltage regulator module. The substrate includes a first side, a second side, and a vertical interconnect access (via) extending between the first side and the second side. The ASIC is mounted on the first side of the substrate in alignment with the via. The voltage regulator module is mounted on the second side of the substrate in alignment with the via so that the voltage regulator module is electrically coupled to the ASIC through the via.
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公开(公告)号:US09859130B2
公开(公告)日:2018-01-02
申请号:US14568084
申请日:2014-12-11
Applicant: Unimicron Technology Corp.
Inventor: Dyi-Chung Hu , Ming-Chih Chen , Tzyy-Jang Tseng
CPC classification number: H01L21/481 , C25D1/003 , H05K1/113 , H05K3/424 , H05K3/4647 , H05K3/4682 , H05K2201/10378 , H05K2203/0152 , H05K2203/0726 , H05K2203/0733 , Y10T29/49155 , Y10T156/10
Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.
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公开(公告)号:US20170372994A1
公开(公告)日:2017-12-28
申请号:US15700483
申请日:2017-09-11
Applicant: Invensas Corporation
Inventor: Rajesh Katkar , Cyprian Emeka Uzoh , Belgacem Haba , Ilyas Mohammed
IPC: H01L23/498 , H01L25/065 , H01L23/373 , H01L23/538 , H01L23/00 , H01L21/48
CPC classification number: H05K1/0306 , H01L21/481 , H01L21/4853 , H01L21/486 , H01L23/13 , H01L23/3731 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L23/5381 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06572 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H05K1/09 , H05K1/112 , H05K1/115 , H05K3/4007 , H05K3/42 , H05K2201/09545 , H05K2201/10378 , H05K2203/0323
Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.
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公开(公告)号:US20170372991A1
公开(公告)日:2017-12-28
申请号:US15624080
申请日:2017-06-15
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor: KOSUKE TSUKAMOTO , NORIYOSHI SHIMIZU
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L23/49822 , H01L21/481 , H01L21/4857 , H01L21/486 , H01L23/145 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H05K1/141 , H05K3/0055 , H05K3/4602 , H05K2201/10378 , H01L2924/00
Abstract: A wiring substrate includes a first wiring layer, an insulative resin first insulation layer covering the first wiring layer, and a second wiring layer located on an upper surface of the first insulation layer. A via wiring layer, which extends through the first insulation layer to connect the first and second wiring layers, includes an upper end surface connected to the second wiring layer and flush with the upper surface of the first insulation layer. The second wiring layer has a higher wiring density than the first wiring layer. The first insulation layer includes a first resin layer and a second resin layer located on an upper surface of the first resin layer and having a lower filler content rate than the first resin layer. The upper surface of the first resin layer is a curved surface upwardly curved toward the upper end surface of the via wiring layer.
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公开(公告)号:US09853002B2
公开(公告)日:2017-12-26
申请号:US15295094
申请日:2016-10-17
Applicant: Renesas Electronics Corporation
Inventor: Shuuichi Kariyazaki
IPC: H01L23/64 , H01L23/66 , H01L23/498 , H05K1/02 , H01L23/538 , H01L23/50 , H01L23/522 , H05K1/18
CPC classification number: H01L23/642 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5222 , H01L23/5383 , H01L23/66 , H01L2223/6627 , H01L2223/6661 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311 , H01L2924/30111 , H05K1/0231 , H05K1/181 , H05K2201/10378
Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.
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公开(公告)号:US09842813B2
公开(公告)日:2017-12-12
申请号:US14860565
申请日:2015-09-21
Applicant: Altera Corporation
Inventor: Xiaohong Jiang , Yuanlin Xie
IPC: H05K1/18 , H01L23/66 , H05K1/02 , H01P3/08 , H05K1/14 , H01L23/13 , H01L23/36 , H01L23/538 , H01L23/00
CPC classification number: H01L23/66 , H01L23/13 , H01L23/36 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/73 , H01L2223/6627 , H01L2224/131 , H01L2224/16227 , H01L2224/73253 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01P3/081 , H05K1/0243 , H05K1/025 , H05K1/141 , H05K1/183 , H05K3/3436 , H05K2201/10378 , H01L2924/014 , H01L2924/00014
Abstract: In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.
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公开(公告)号:US09839133B2
公开(公告)日:2017-12-05
申请号:US14730250
申请日:2015-06-04
Applicant: APPLE INC.
Inventor: Meng Chi Lee , Shankar Pennathur , Scott L. Gooch , Dennis R. Pyper , Amir Salehi
CPC classification number: H05K1/189 , H01L23/4012 , H01L25/0652 , H01L25/0655 , H05K1/141 , H05K1/144 , H05K1/181 , H05K3/284 , H05K3/361 , H05K3/4015 , H05K2201/10318 , H05K2201/10378 , H05K2203/1316 , Y10T29/49128
Abstract: Readily modifiable and customizable, low-area overhead interconnect structures for forming connections between a system-in-a-package module and other components in an electronic device. One example may provide an interposer for providing an interconnection between a system-in-a-package module and other components in an electronic device. Another may provide a plurality of conductive pins or contacts to form interconnect paths between a module and other components.
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公开(公告)号:US20170330677A1
公开(公告)日:2017-11-16
申请号:US15152177
申请日:2016-05-11
Applicant: Cascade Microtech, Inc.
Inventor: Jay Salmon , Roy E. Swart , Brandon Liew
CPC classification number: H01F27/2804 , G01R1/07378 , G01R3/00 , G01R31/2889 , H01F41/041 , H05K3/368 , H05K3/4007 , H05K2201/10378
Abstract: Space transformers, planarization layers for space transformers, methods of fabricating space transformers, and methods of planarizing space transformers are disclosed herein. In one embodiment, the space transformers include a space transformer assembly including a first rigid space transformer layer, a second rigid space transformer layer, and an attachment layer that extends between the first rigid space transformer layer and the second rigid space transformer layer. In another embodiment, the space transformers include a space transformer body and a flex cable assembly. The planarization layer includes an interposer, a resilient dielectric layer, a planarized rigid dielectric layer, a plurality of holes, and an electrically conductive paste extending within the plurality of holes. In one embodiment, the methods include methods of fabricating the space transformer assembly. In another embodiment, the methods include methods of planarizing a space transformer.
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