公开(公告)号：US10242144B1

公开(公告)日：2019-03-26

申请号：US15338134

申请日：2016-10-28

Applicant: Altera Corporation

Inventor： Saurabh Adya ,  Mahesh A. Iyer ,  Love Singhal

IPC: G06F17/50

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be defined as a hardware resource pair. The hardware resource pair may define an overlap region, with which a cost function may be associated. The cost function may be minimized in conjunction with other types of cost functions using a solver. The solver may generate coordinates that minimize or remove overlap to be implemented in the optimal design.

公开(公告)号：US10235485B1

公开(公告)日：2019-03-19

申请号：US15277376

申请日：2016-09-27

Applicant: Altera Corporation

Inventor： Mahesh A. Iyer ,  Kalen B. Brunham

IPC: G06F17/50

Abstract: Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.

公开(公告)号：US10224934B1

公开(公告)日：2019-03-05

申请号：US15352406

申请日：2016-11-15

Applicant: Altera Corporation

Inventor： Doris Tzu Lang Chen ,  Deshanand Singh

IPC: H03K19/173 ,  H03K19/177

Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.

公开(公告)号：US10223493B1

公开(公告)日：2019-03-05

申请号：US15195517

申请日：2016-06-28

Applicant: Altera Corporation

Inventor： Athanasius Spyrou

IPC: G06F17/50

Abstract: Electronic design automation tools may perform static timing analysis on an integrated circuit design. An integrated circuit design may have multiple nodes that can be traversed using a breadth-first search. To reduce the run-time of static timing analysis tools, tags recording arrival times associated with non-critical paths may have their consolidated in order to include only the critical timing information in the tag, thereby reducing the amount of data that is carried through to the analysis of the entire design. In a critical slack based merging method, a maximal arrival time associated with a circuit node may be compared to the remaining arrival times associated with the circuit node. Arrival times less than the maximal arrival time by an amount greater than a threshold amount may be deemed non-critical arrival times and may be removed from the tag for the circuit node.

公开(公告)号：US20190065188A1

公开(公告)日：2019-02-28

申请号：US16154517

申请日：2018-10-08

Applicant: ALTERA CORPORATION

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/28 ,  G06F17/50 ,  G06F17/14 ,  G06F9/54

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US10169065B1

公开(公告)日：2019-01-01

申请号：US15197260

申请日：2016-06-29

Applicant: Altera Corporation

Inventor： Jeffrey L. Nye ,  Shiva Rao

IPC: G06F9/445 ,  G06F9/455 ,  G06F8/61 ,  H04L29/08 ,  G06F9/48

Abstract: Live migration of a hardware accelerated application may be orchestrated by cloud services to transfer the application from a source server to a destination server. The live migration may be triggered by probe circuitry that monitors quality of service metrics for migration conditions at the source server. When live migration is initiated by the cloud services, a snapshot of all state information relevant to the application at the source server may be saved to network attached storage accessible by the destination server. Changes to said state information at the source server may be mirrored onto the network attached storage. The destination server may copy the snapshot and subsequent changes and run the application in parallel before taking complete control of the application. After a handshake operation between the source and destination servers, the application may be shut down at the source server.

公开(公告)号：US10146249B2

公开(公告)日：2018-12-04

申请号：US15274597

申请日：2016-09-23

Applicant: Altera Corporation

Inventor： Han Hua Leong ,  Ru Yin Ng ,  Geok Sun Chong ,  David W. Mendel

IPC: H04L7/00 ,  G06F1/08 ,  G06F13/40

Abstract: A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

公开(公告)号：US10140411B2

公开(公告)日：2018-11-27

申请号：US15356791

申请日：2016-11-21

Applicant: Altera Corporation

Inventor： Vaughn Betz ,  Jordan Swartz ,  Vadim Gouterman

IPC: G06F17/50

Abstract: A method for designing a system to be implemented on a target device, the method including generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing a corresponding net in the bounding box. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

公开(公告)号：US20180337681A1

公开(公告)日：2018-11-22

申请号：US16051341

申请日：2018-07-31

Applicant: Altera Corporation

Inventor： Tony K. Ngai

IPC: H03K19/0175 ,  H03K19/177 ,  H01L25/065 ,  G06F17/50 ,  H01L23/538

Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.

公开(公告)号：US20180321909A1

公开(公告)日：2018-11-08

申请号：US16039029

申请日：2018-07-18

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/487 ,  G06F7/485

CPC classification number: G06F7/4876 ,  G06F7/485 ,  G06F2207/3816 ,  G06F2207/382 ,  G06F2207/483

Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.