公开(公告)号：US20180057353A1

公开(公告)日：2018-03-01

申请号：US15806074

申请日：2017-11-07

Applicant: Amkor Technology, Inc.

Inventor： Jae Ung Lee ,  Byong Jin Kim ,  Young Seok Kim ,  Wook Choi ,  Seung Jae Yoo ,  Yung Woo Lee ,  EunNaRa Cho ,  Dong Hyun Bang

IPC: B81B3/00 ,  B81C1/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/28 ,  H01L21/56

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H01L21/568 ,  H01L23/055 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/562 ,  H01L24/83 ,  H01L24/97 ,  H01L25/065 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/16152

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

公开(公告)号：US09881864B2

公开(公告)日：2018-01-30

申请号：US15477853

申请日：2017-04-03

Applicant: Amkor Technology, Inc.

Inventor： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

公开(公告)号：US20170194239A1

公开(公告)日：2017-07-06

申请号：US15149436

申请日：2016-05-09

Applicant: Amkor Technology, Inc.

Inventor： Ji Yeon Ryu ,  Byong Jin Kim ,  Jae Beum Shim

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/81 ,  H01L2021/60022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81224 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81471 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device with etched grooves for embedded devices is disclosed and may, for example, include a substrate comprising a top surface and a bottom surface, a groove extending into the substrate from the bottom surface, and a redistribution structure in the substrate between the top surface and the bottom surface of the substrate. A semiconductor die may, for example, be coupled to the top surface of the substrate. An electronic device may, for example, be at least partially within the groove and electrically coupled to the redistribution structure. A conductive pad may, for example, be on the bottom surface of the substrate. A conductive bump may, for example, be on the conductive pad. The electronic device in the groove may, for example, extend beyond the bottom surface of the substrate a distance that is less than a height of the conductive bump from the bottom surface of the substrate. An encapsulant may, for example, encapsulate the semiconductor die and the top surface of the substrate. The electronic device may, for example, comprise a capacitor.

公开(公告)号：US09631481B1

公开(公告)日：2017-04-25

申请号：US15293524

申请日：2016-10-14

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Jae Min Bae ,  Byong Jin Kim ,  Won Bae Bang

IPC: H01L33/62 ,  E21B47/10 ,  G01N29/024 ,  E21B49/00 ,  E21B21/08

CPC classification number: H01L23/564 ,  C08G77/14 ,  C08L83/06 ,  C08L2205/025 ,  E21B21/08 ,  E21B47/101 ,  E21B49/005 ,  G01N29/024 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L33/56 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/181 ,  C08L83/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.

公开(公告)号：US20170069558A1

公开(公告)日：2017-03-09

申请号：US15173379

申请日：2016-06-03

Applicant: Amkor Technology, Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/29 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L21/4839 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49579 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/562 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/91 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/05026 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

Abstract translation: 封装的半导体器件包括具有表面光洁度层的可路由模制引线框架结构。 在一个实施例中，可路由模制的引线框架结构包括包括表面光洁度层的第一层压层，连接到表面光洁度层的通孔和覆盖露出的表面光洁度层顶表面的通孔的第一树脂层。 第二层叠层包括连接到通孔的第二导电图案，连接到第二导电图案的凸块焊盘以及覆盖第一树脂层的一侧的第二树脂层，第二导电图案和凸块焊盘。 半导体管芯与表面处理层电连接，密封剂覆盖半导体管芯和第一树脂层的另一侧。 表面光洁度层提供可定制和改进的接合结构，用于将半导体管芯连接到可路由的模制引线框架结构。

公开(公告)号：US20160343688A1

公开(公告)日：2016-11-24

申请号：US15133081

申请日：2016-04-19

Applicant: Amkor Technology Inc.

Inventor： Won Bae Bang ,  Ju Hoon Yoon ,  Ji Young Chung ,  Byong Jin Kim ,  Gi Jeong Kim ,  Choon Heung Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/0105

Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

Abstract translation: 在一个实施例中，制造半导体封装的方法包括提供多层模制的导电结构。 多层模制导电结构包括设置在载体的表面上的第一导电结构和覆盖第一导电结构的至少一部分的第一密封剂，而其它部分暴露在第一密封剂中。 第二导电结构设置在第一密封剂上并电连接到第一导电结构。 第二密封剂覆盖第二导电结构的第一部分，而第二导电结构的第二部分暴露于外部，并且第二导电结构的第三部分暴露在设置在第二密封剂中的接收空间中。 该方法包括将半导体管芯电连接到第二导电结构，并且在一些实施例中，去除载体。

公开(公告)号：US20160276236A1

公开(公告)日：2016-09-22

申请号：US14984064

申请日：2015-12-30

Applicant: Amkor Technology, Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4828 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49861 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.

Abstract translation: 在一个实施例中，电子封装包括具有嵌入在绝缘层内的多个焊盘的衬底。 导电图案设置在相应的陆地顶表面的至少一部分上。 电子设备电连接到导电图案和封装绝缘材料和电子设备的顶表面的封装体，其中底部表面暴露于外部。 在另一个实施例中，绝缘层的顶部表面和顶部表面基本上是共面的，并且导电图案进一步与绝缘层顶表面的部分重叠。

公开(公告)号：US20160172277A1

公开(公告)日：2016-06-16

申请号：US15043572

申请日：2016-02-14

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Jae Min Bae ,  Hyung Il Jeon ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/50

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2021/60007 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Abstract translation: 在一个实施例中，用于形成封装衬底的方法包括选择性地去除引线框架的部分以形成空腔并用树脂层填充空腔以限定粘合垫和焊盘结构。 引线框架的顶部部分被选择性地移除以将粘合垫和焊盘结构彼此隔离，以暴露树脂层的顶表面，并且形成至少一个具有比尺寸相对更大的部分的焊盘 的相应下部。

公开(公告)号：US09293398B2

公开(公告)日：2016-03-22

申请号：US14072845

申请日：2013-11-06

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Jae Min Bae ,  Hyung Il Jeon ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49548 ,  H01L23/49861 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/92247 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Abstract translation: 在一个实施例中，用于形成封装衬底的方法包括选择性地去除引线框架的部分以形成空腔并用树脂层填充空腔以限定粘合垫和焊盘结构。 引线框架的顶部部分被选择性地移除以将粘合垫和焊盘结构彼此隔离，以暴露树脂层的顶表面，并且形成至少一个具有比尺寸相对更大的部分的焊盘 的相应下部。

公开(公告)号：US20150371933A1

公开(公告)日：2015-12-24

申请号：US14839956

申请日：2015-08-29

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Hyeong Il Jeon ,  Hyung Kook Chung ,  Hong Bae Kim ,  Byong Jin Kim

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/3114 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00014

Abstract: In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.

Abstract translation: 在一个实施例中，微引线框架结构包括形成在引线和/或连接结构上的一个或多个刚度增强结构。 刚性加强结构可以通过将微引线框架的预定部分留在包括例如内引线的一部分，外引线的一部分以及连接条的部分，其组合和其它结构的整个厚度来形成。 刚度增强结构被配置为减少由组装过程引起的变形缺陷和电短缺。