公开(公告)号：US20220375865A1

公开(公告)日：2022-11-24

申请号：US17323253

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Krishna Bharath ,  Sai Vadlamani ,  Pooya Tadayon ,  Tarek A. Ibrahim

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/64 ,  H01L25/065

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.

公开(公告)号：US11329358B2

公开(公告)日：2022-05-10

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US11227825B2

公开(公告)日：2022-01-18

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/03 ,  H05K1/16 ,  H01F17/00 ,  H01F17/06 ,  H01L21/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48 ,  H01L23/60 ,  G11B5/17 ,  G11B5/31 ,  G11B5/147 ,  G11B5/187 ,  H01L23/498 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US11189580B2

公开(公告)日：2021-11-30

申请号：US16721327

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H05K1/18 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

公开(公告)号：US20210098436A1

公开(公告)日：2021-04-01

申请号：US16635147

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/64

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US20200066627A1

公开(公告)日：2020-02-27

申请号：US16108953

申请日：2018-08-22

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48 ,  H01L23/522 ,  H01L23/58 ,  H01L49/02 ,  H01L23/64

Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

公开(公告)号：US20200013770A1

公开(公告)日：2020-01-09

申请号：US16030196

申请日：2018-07-09

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Krishna Bharath ,  Mathew Manusharow

IPC: H01L27/01 ,  H01L23/498 ,  H01L49/02

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200004282A1

公开(公告)日：2020-01-02

申请号：US16020725

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Krishna Bharath

IPC: G05F1/46 ,  H01L25/18 ,  H02M3/158 ,  H01L49/02

Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.

公开(公告)号：US20190259705A1

公开(公告)日：2019-08-22

申请号：US16335845

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Henning Braunisch ,  Krishna Bharath ,  Javier Soto Gonzalez ,  Javier A. Falcon

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US09992859B2

公开(公告)日：2018-06-05

申请号：US14866693

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08

CPC classification number: H05K1/0245 ,  H01P3/02 ,  H01P3/026 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.