公开(公告)号：US20210391266A1

公开(公告)日：2021-12-16

申请号：US16902768

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Jason M. Gamba ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Omkar G. Karhade ,  Bai Nie ,  Gang Duan ,  Kristof Kuwawi Darmawikarta ,  Wei-Lun Jen

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US10672626B2

公开(公告)日：2020-06-02

申请号：US15469284

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Aditya S. Vaidya ,  Nachiket R. Raravikar ,  Eric J. Li

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

公开(公告)号：US10595409B2

公开(公告)日：2020-03-17

申请号：US15628430

申请日：2017-06-20

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Ravindranath Mahajan ,  John S. Guzek ,  Nitin A. Deshpande

IPC: H01L25/00 ,  H05K1/14 ,  H01L23/552 ,  H01L23/13 ,  H01L23/498 ,  H05K1/02 ,  H01L25/065 ,  H05K3/36

Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

公开(公告)号：US10256198B2

公开(公告)日：2019-04-09

申请号：US15468067

申请日：2017-03-23

Applicant: INTEL CORPORATION

Inventor： Eric J. Li ,  Guotao Wang ,  Huiyang Fei ,  Sairam Agraharam ,  Omkar G. Karhade ,  Nitin A. Deshpande

IPC: H01L23/12 ,  H01L23/053 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H05K3/30 ,  H05K3/34 ,  H01L21/48 ,  H05K1/18

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US20170330835A1

公开(公告)日：2017-11-16

申请号：US15668179

申请日：2017-08-03

Applicant: INTEL CORPORATION

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L23/522

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L23/13 ,  H01L23/522 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/15192

Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.

公开(公告)号：US20170290155A1

公开(公告)日：2017-10-05

申请号：US15628430

申请日：2017-06-20

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Ravindranath Mahajan ,  John S. Guzek ,  Nitin A. Deshpande

IPC: H05K1/14 ,  H01L25/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/49833 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/361 ,  H05K2201/09245 ,  H05K2201/09681 ,  Y10T29/49126

Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

公开(公告)号：US09685388B2

公开(公告)日：2017-06-20

申请号：US15296995

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Jiro Kubota ,  Omkar G. Karhade ,  Shawna M. Liff ,  Kinya Ichikawa ,  Nitin A. Deshpande

IPC: H01L23/18 ,  H01L21/56 ,  H01L25/10 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/18 ,  H01L21/566 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.

公开(公告)号：US20160343666A1

公开(公告)日：2016-11-24

申请号：US15114036

申请日：2014-02-26

Applicant: INTEL CORPORATION

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L23/13 ,  H01L23/522 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15153 ,  H01L2924/15192

Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.

Abstract translation: 微电子结构包括具有第一表面和从衬底第一表面延伸到衬底中的空腔的衬底，附接到衬底第一表面的第一微电子器件和第二微电子器件，以及设置在衬底腔内并附接到 第一微电子器件和第二微电子器件。 桥包括从桥的第一表面延伸到相对的第二表面的多个导电通孔，其中导电通孔电耦合以将电信号从基板传递到第一微电子器件和第二微电子器件。 该桥进一步在第一微电子器件和第二微电子器件之间产生至少一个电信号连接。

公开(公告)号：US09502368B2

公开(公告)日：2016-11-22

申请号：US14571623

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Jiro Kubota ,  Omkar G. Karhade ,  Shawna M. Liff ,  Kinya Ichikawa ,  Nitin A. Deshpande

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/18 ,  H01L21/566 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.

Abstract translation: 微电子封装可以形成有围绕微电子管芯的图框加强件，以减少微电子封装的翘曲。 用于制造这种微电子封装的实施例可以包括形成具有有源表面和相对背面的微电子管芯，其中微电子管芯有源表面可以附接到微电子衬底。 可以形成具有穿过其中的开口的相框加强件并将其放置在脱模膜上，其中模塑材料可以沉积在画框加强件和释放膜上。 微电子管芯可以插入模具材料中，其中微电子管芯的至少一部分延伸到相框开口中。 可以去除剥离膜，然后可以移除在微电子管芯背表面上延伸的一部分模具材料以形成微电子封装。

公开(公告)号：US20250112205A1

公开(公告)日：2025-04-03

申请号：US18478950

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  Surhud V. Khare

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid bonding on the bottom surface of the die. Embedded bridges or chiplets or not used for die-to-die I/O routing, which can free up space for more through-dielectric vias to provide power and ground connections to the die, which can provide for improved power delivery.