公开(公告)号：US20240114627A1

公开(公告)日：2024-04-04

申请号：US17937894

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Robert Alan May ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Brandon C. Marin

IPC: H05K3/06 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09

CPC classification number: H05K3/062 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H05K1/09 ,  H05K3/067 ,  H01L25/0652

Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

公开(公告)号：US20240113087A1

公开(公告)日：2024-04-04

申请号：US17957403

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Gang Duan ,  Srinivas Pietambaram ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Debendra Mallik ,  Ravindranath Mahajan ,  Rahul Manepalli

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/13 ,  H01L23/16 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16235 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1094

Abstract: An apparatus is provided which comprises: an interposer comprising glass, one or more redistribution layers on a first interposer surface, one or more conductive contacts on a second interposer surface opposite the first interposer surface, one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the redistribution layers on the first interposer surface, an integrated circuit device embedded within a cavity in the interposer between the first and second interposer surfaces, the embedded integrated circuit device coupled with a first redistribution layers surface, a stack of two or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface, and mold material surrounding at least one side of the stack of two or more integrated circuit devices. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240006327A1

公开(公告)日：2024-01-04

申请号：US17856663

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Robert A. May ,  Brandon Marin ,  Benjamin Duong ,  Suddhasattwa Nad ,  Hsin-Wei Wang ,  Leonel Arana ,  Darko Grujicic

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/08

Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.

公开(公告)号：US11791228B2

公开(公告)日：2023-10-17

申请号：US16380486

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Darmawikarta ,  Roy Dittler ,  Jeremy Ecton ,  Darko Grujicic

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/488

CPC classification number: H01L23/3114 ,  H01L23/3128 ,  H01L23/488

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

公开(公告)号：US11622448B2

公开(公告)日：2023-04-04

申请号：US16505403

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Srinivas Pietambaram ,  Andrew J. Brown ,  Gang Duan ,  Jeremy Ecton ,  Sheng C. Li

IPC: H05K1/11 ,  H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K3/40 ,  H05K3/28

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

公开(公告)号：US20230078099A1

公开(公告)日：2023-03-16

申请号：US17473414

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Gang Duan ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bai Nie

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L21/48

Abstract: A substrate of a microelectronic assembly is provided, the substrate comprising conductive traces through an organic dielectric, and a coating comprising silicon and oxygen. The substrate is configured to couple with a component electrically and mechanically by at least one or more conductive via through the coating, the conductive via being electrically connected to the conductive traces, such that the coating is between the organic dielectric and the component when coupled. In some embodiments, the component includes another coating comprising silicon and oxygen, with conductive vias through the second coating. The conductive vias and the coating of the substrate are configured to bind with the conductive vias and the coating of the component respectively to form hybrid bonds.

公开(公告)号：US11116084B2

公开(公告)日：2021-09-07

申请号：US16634804

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US10515824B2

公开(公告)日：2019-12-24

申请号：US15868942

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Leonel Arana ,  Nicholas S. Haehn ,  Hsin-Wei Wang ,  Oscar Ojeda ,  Arnab Roy

IPC: H01L21/321 ,  H01L21/3213 ,  C23F1/14 ,  H01L21/48

Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.

公开(公告)号：US20190304890A1

公开(公告)日：2019-10-03

申请号：US15942864

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Kristof Kuwawi Darmawikarta ,  Oscar Ojeda ,  Arnab Roy ,  Nicholas Haehn

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L21/48 ,  H01L21/027 ,  G03F7/039 ,  G03F7/038 ,  G03F7/20 ,  G03F7/26

Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.

公开(公告)号：US20250112165A1

公开(公告)日：2025-04-03

申请号：US18478250

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Hiroki Tanaka ,  Robert May ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Numair Ahmed ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Bai Nie ,  Haobo Chen ,  Xiao Liu ,  Bohan Shan ,  Shruti Sharma ,  Mollie Stewart

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.