公开(公告)号：US20230282579A1

公开(公告)日：2023-09-07

申请号：US18318295

申请日：2023-05-16

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L21/311 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/535 ,  H01L21/311 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

公开(公告)号：US20230135326A1

公开(公告)日：2023-05-04

申请号：US17647053

申请日：2022-01-05

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： LinChun WU ,  Wenxi ZHOU ,  Zhiliang XIA ,  ZongLiang HUO

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.

公开(公告)号：US20220366985A1

公开(公告)日：2022-11-17

申请号：US17709651

申请日：2022-03-31

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Di WANG ,  Wenxi ZHOU ,  Tingting ZHAO ,  Zhiliang XIA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.

公开(公告)号：US20220115322A1

公开(公告)日：2022-04-14

申请号：US17093170

申请日：2020-11-09

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong ZHANG ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.

公开(公告)号：US20220037354A1

公开(公告)日：2022-02-03

申请号：US17451583

申请日：2021-10-20

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong ZHANG ,  Zhongwang SUN ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zhi ZHANG

IPC: H01L27/11582 ,  G11C8/14 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565

Abstract: In a method for fabricating a semiconductor device, an initial stack of alternatingly sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. A connection region, a first staircase region, and a second staircase region are patterned in the initial stack. The first staircase region is shaped in the initial stack to form a first staircase, and the second staircase region is shaped in the initial stack to form a second staircase. The first staircase is formed in a first block of the initial stack and extends between first array regions of the first block. The second staircase is formed in a second block of the initial stack and extends between second array regions of the second block. The connection region is formed in the initial stack between the first staircase and the second staircase.

公开(公告)号：US20220028888A1

公开(公告)日：2022-01-27

申请号：US17495252

申请日：2021-10-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong ZHANG ,  Wenyu HUA ,  Bo HUANG ,  Zhiliang XIA

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/1157

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes an upper staircase structure and a lower staircase structure, wherein the upper staircase structure is formed in the first film stack and the lower staircase structure is formed in the second film stack. The upper and lower staircase structures are next to each other with an offset.

公开(公告)号：US20220013459A1

公开(公告)日：2022-01-13

申请号：US17449134

申请日：2021-09-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

公开(公告)号：US20210384219A1

公开(公告)日：2021-12-09

申请号：US17190601

申请日：2021-03-03

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Yonggang YANG ,  Kun ZHANG ,  Hao ZHANG ,  Yiming AI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/00

Abstract: Aspects of the disclosure provide a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device can include forming a stack of alternating first insulating layers and first sacrificial layers over a semiconductor substrate, and forming a staircase in the stack having a plurality of steps, with at least a first step of the staircase including a first sacrificial layer of the first sacrificial layers over a first insulating layer of the first insulating layers. Further, the method can include forming a recess in the first sacrificial layer, forming a second sacrificial layer in the recess, and replacing a portion of the first sacrificial layer and the second sacrificial layer with a conductive material that forms a contact pad.

公开(公告)号：US20210375368A1

公开(公告)日：2021-12-02

申请号：US17113582

申请日：2020-12-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C16/30

Abstract: Aspects of the disclosure provide a method for data erase in a memory device. The method includes providing first erase carriers from a body portion for the memory cell string, during an erase operation in a memory cell string. The first erase carriers flow in a first direction from a source side of the memory cell string to a drain side of the memory cell string. Further, the method includes providing second erase carriers from a junction at the drain side of the memory cell string. The second erase carriers flow in a second direction from the drain side of the memory cell string to the source side of the memory cell string. Then, the method includes injecting the first erase carriers and the second erase carriers to charge storage portions of the memory cells in the memory cell string.

公开(公告)号：US20210257220A1

公开(公告)日：2021-08-19

申请号：US16909537

申请日：2020-06-23

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L21/311 ,  H01L21/8234

Abstract: Staircase structures for a three-dimensional (3D) memory device are disclosed. In some embodiments, the method includes disposing an alternating dielectric stack on a substrate with first and second dielectric layers alternatingly stacked on top of each other. Next, multiple division blocks can be formed in a staircase region. Each division block includes a first plurality of staircase steps in the first direction. Each staircase step in the first direction has two or more dielectric layer pairs. Then, a second plurality of staircase steps along a second direction, perpendicular to the first direction, can be formed. Each staircase step in the second direction includes the first plurality of staircase steps along the first direction. The method further includes forming an offset number of dielectric layer pairs between the multiple division blocks such that each dielectric layer pair is accessible from a top surface of a staircase step.