公开(公告)号：US09218970B2

公开(公告)日：2015-12-22

申请号：US14642968

申请日：2015-03-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer Lin ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  B81C1/00 ,  H01L21/02 ,  H01L21/768

CPC classification number: B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract translation: 在半导体器件制造期间在形成互连的镶嵌工艺中形成氮化钛（TiN）硬掩模的方法，同时控制由TiN硬掩模承载的应力的类型和大小。 TiN硬掩模以多层结构形成，其中通过重复包括TiN和氯PECVD沉积以及N2 / H2等离子体气体处理的工艺循环来连续形成每个子层。 在其形成期间，通过控制TiN子层的数量和等离子体气体处理持续时间来控制由TiN硬掩模承载的应力，使得应力可以平衡在常规制备的TiN硬掩模上预期的预定外部应力 ，这导致沟槽侧壁变形，沟槽开口收缩和间隙填充问题。

公开(公告)号：US09212054B1

公开(公告)日：2015-12-15

申请号：US14515480

申请日：2014-10-15

Applicant: Microlux Technology

Inventor： Tom Kwa

IPC: H01L21/50 ,  G01L9/06 ,  B81C1/00 ,  G01L9/00

CPC classification number: B81C1/00674 ,  B81B2201/0264 ,  B81C1/00047 ,  B81C1/00158 ,  B81C1/00277 ,  B81C1/00357 ,  B81C1/00373 ,  B81C1/00396 ,  B81C2201/0132 ,  G01L9/0045 ,  G01L19/0618

Abstract: A pressure sensor assembly comprising: three stacked silicon wafers which form a support, a sensor and a cover wherein the sensor includes a cavity extending from the bottom of the sensor up towards the top of the sensor to form a cavity bottom and a diaphragm; a dielectric layer covering the bottom of the sensor and the cavity and wherein the support is coupled to the dielectric layer along the bottom of the sensor; a plurality of ports located on a top of the support within an area defined by the cavity, the plurality of ports extending through the support to its bottom and wherein the cover is coupled to the top of the sensor covering the diaphragm; and, a second cavity cut into a bottom of the cover wherein the second cavity is sized and positioned to surround the diaphragm.

Abstract translation: 一种压力传感器组件，包括：三个堆叠的硅晶片，其形成支撑件，传感器和盖，其中所述传感器包括从所述传感器的底部向上朝向所述传感器的顶部延伸的空腔，以形成空腔底部和隔膜; 覆盖传感器底部和空腔的电介质层，并且其中所述支撑件沿着所述传感器的底部耦合到所述电介质层; 多个端口，其位于由所述空腔限定的区域内的所述支撑件的顶部上，所述多个端口通过所述支撑件延伸到其底部，并且其中所述盖联接到覆盖所述隔膜的所述传感器的顶部; 以及切割到所述盖的底部中的第二腔，其中所述第二腔的尺寸设置成围绕所述隔膜。

公开(公告)号：US09187319B2

公开(公告)日：2015-11-17

申请号：US14366488

申请日：2012-06-04

Applicant: Gang Wei ,  Chun Wang ,  Dongsan Li

Inventor： Gang Wei ,  Chun Wang ,  Dongsan Li

IPC: H01L21/311 ,  B81C1/00 ,  H01L21/3065 ,  B81C99/00

CPC classification number: B81C1/00531 ,  B81C1/00619 ,  B81C99/0025 ,  B81C2201/0132 ,  H01L21/30655

Abstract: A substrate etching method and a substrate processing device, the substrate etching method includes: S1: placing a substrate to be processed into a reaction chamber; S2: supplying etching gas into the reaction chamber; S3: turning on an excitation power supply to generate plasma in the reaction chamber; S4: turning on a bias power supply to apply bias power to the substrate; S5: turning off the bias power supply, and meanwhile, starting to supply deposition gas into the reaction chamber; S6: stopping supply of the deposition gas into the reaction chamber, and meanwhile, turning on the bias power supply; S7: repeating steps S5-S6, until the etching process is completed. In the whole etching process, the etching operation is always performed, and the deposition operation is performed sometimes. Therefore, during the deposition operation, the plasma in the reaction chamber can etch away at least a part of deposited polymers formed by the deposition operation on a sidewall of an etched section, so that the sidewall of the etched section of the substrate is smooth.

Abstract translation: 基板蚀刻方法和基板处理装置，基板蚀刻方法包括：S1：将待处理的基板放置在反应室中; S2：向反应室供给蚀刻气体; S3：打开激励电源以在反应室中产生等离子体; S4：打开偏置电源以向基板施加偏置功率; S5：关闭偏压电源，同时开始向反应室供应沉积气体; S6：停止向反应室供应沉积气体，同时打开偏置电源; S7：重复步骤S5-S6，直到蚀刻处理完成。 在整个蚀刻过程中，总是执行蚀刻操作，并且有时执行沉积操作。 因此，在沉积操作期间，反应室中的等离子体可以蚀刻掉在蚀刻部分的侧壁上通过沉积操作形成的沉积聚合物的至少一部分，从而衬底的蚀刻部分的侧壁是光滑的。

公开(公告)号：US20150311091A1

公开(公告)日：2015-10-29

申请号：US14646909

申请日：2013-11-01

Applicant: Beijing NMC Co., Ltd.

Inventor： Zhongwei JIANG

IPC: H01L21/3213

CPC classification number: H01L21/32137 ,  B81C1/00531 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: Embodiments of the invention provide a substrate etching method, which includes: a deposition operation for depositing a polymer on a side wall of a silicon groove, an etching operation for etching the side wall of the silicon groove, and repeating the deposition operation and the etching operation at least twice. In the process of completing all cycles of the etching operation, a chamber pressure of a reaction chamber is decreased from a preset highest pressure to a preset lowest pressure according to a preset rule. The substrate etching method, according to various embodiments of the invention, avoid the problem of damaging the side wall, thereby making the side wall smooth.

Abstract translation: 本发明的实施例提供了一种基板蚀刻方法，其包括：用于在硅槽的侧壁上沉积聚合物的沉积操作，用于蚀刻硅槽的侧壁的蚀刻操作，以及重复沉积操作和蚀刻 操作至少两次。 在完成蚀刻操作的所有循环的过程中，根据预设规则，反应室的室压力从预设的最高压力降低到预设的最低压力。 根据本发明的各种实施例的基板蚀刻方法避免了损坏侧壁的问题，从而使侧壁平滑。

公开(公告)号：US20150183631A1

公开(公告)日：2015-07-02

申请号：US14644937

申请日：2015-03-11

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.

Abstract translation: 根据半导体器件的实施例，半导体器件包括布置在微机械结构上的微机械结构和半导体材料。 半导体材料的侧表面包括第一区域和第二区域。 第一区域具有起伏，第二区域是侧表面的周边区域，朝向微机械结构减小。

公开(公告)号：US20150140823A1

公开(公告)日：2015-05-21

申请号：US14411931

申请日：2013-09-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jiale Su

IPC: B81C1/00

CPC classification number: B81C1/00396 ,  B81B2203/033 ,  B81C1/00412 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0132 ,  H01L21/3086

Abstract: A silicon etching method of etching a silicon substrate to form silicon trenches having different width dimensions includes: S1, providing a silicon substrate; S2, depositing a mask layer on the silicon substrate; S3, corroding the mask layer to form windows having different width dimensions, wherein a mask layer having a certain thickness is reserved at least at a bottom portion of a window having a non-minimum width dimension, such that all the silicon trenches have the same depth after step S4; and S4, corroding the mask layer at the bottom portion of the window and the silicon substrate to form the silicon trenches. The mask layer having a certain thickness is reserved at the bottom portion of the window having the non-minimum width dimension, a relatively large window is protected, and a relatively small window is etched first, so that the finally obtained silicon trenches have the same depth.

Abstract translation: 蚀刻硅衬底以形成具有不同宽度尺寸的硅沟槽的硅蚀刻方法包括：S1，提供硅衬底; S2，在硅衬底上沉积掩模层; S3，腐蚀掩模层以形成具有不同宽度尺寸的窗口，其中具有一定厚度的掩模层至少在具有非最小宽度尺寸的窗口的底部保留，使得所有硅沟槽具有相同的 步骤S4之后的深度; 和S4，腐蚀窗口底部的掩模层和硅衬底以形成硅沟槽。 具有一定厚度的掩模层被保留在具有非最小宽度尺寸的窗口的底部，相对较大的窗口被保护，并且首先蚀刻相对小的窗口，使得最终获得的硅沟槽具有相同的 深度。

公开(公告)号：US20150140717A1

公开(公告)日：2015-05-21

申请号：US14543116

申请日：2014-11-17

Applicant: Robert Bosch GmbH

Inventor： Andrea URBAN

IPC: B81C1/00 ,  B81C99/00

CPC classification number: B81C1/00857 ,  B81C1/00388 ,  B81C1/00531 ,  B81C1/00849 ,  B81C99/0025 ,  B81C2201/0123 ,  B81C2201/0125 ,  B81C2201/0132

Abstract: A method is described for manufacturing a micromechanical structure, in which a structured surface is created in a substrate by an etching method in a first method step, and residues are at least partially removed from the structured surface in a second method step. In the second method step, an ambient pressure for the substrate which is lower than 60 Pa is set and a substrate temperature which is higher than 150° C. is set.

Abstract translation: 描述了一种用于制造微机械结构的方法，其中通过第一方法步骤中的蚀刻方法在衬底中形成结构化表面，并且在第二方法步骤中至少部分地从结构化表面除去残余物。 在第二方法步骤中，设定低于60Pa的基板的环境压力，设定高于150℃的基板温度。

公开(公告)号：US08970940B2

公开(公告)日：2015-03-03

申请号：US13526568

申请日：2012-06-19

Applicant: Takuo Kaitoh ,  Takeshi Kuriyagawa ,  Ryou Sakata ,  Osamu Karikome ,  Timothy J. Brosnihan

Inventor： Takuo Kaitoh ,  Takeshi Kuriyagawa ,  Ryou Sakata ,  Osamu Karikome ,  Timothy J. Brosnihan

IPC: G02B26/00 ,  G02B26/08 ,  B81B7/00

CPC classification number: G02B26/0841 ,  B81B7/007 ,  B81B2201/045 ,  B81C2201/0132 ,  B81C2201/016

Abstract: The MEMS shutter includes a shutter having an aperture part, a first spring connected to the shutter, a first anchor connected to the first spring, a second spring and a second anchor connected to the second spring, an insulation film on a surface of the shutter, the first spring, the second spring, the first anchor and the second anchor, the surfaces being in a perpendicular direction to a surface of a substrate, and the insulation film is not present on a surface of the plurality of terminals, and a surface of the shutter, the first spring, the second spring, the first anchor and the second anchor, the surfaces being in a parallel direction to a surface of the substrate and on the opposite side of the side facing the substrate.

Abstract translation: MEMS快门包括具有开口部分的快门，连接到快门的第一弹簧，连接到第一弹簧的第一锚杆，连接到第二弹簧的第二弹簧和第二锚固件，在挡板的表面上的绝缘膜 所述第一弹簧，所述第二弹簧，所述第一锚固件和所述第二锚固件，所述表面在垂直于基板表面的方向上，并且所述绝缘膜不存在于所述多个端子的表面上，并且所述表面 所述第一弹簧，所述第二弹簧，所述第一锚固件和所述第二锚固件，所述表面在与所述基板的表面平行的方向上以及在面向所述基板的所述一侧的相对侧上。

公开(公告)号：US08945939B2

公开(公告)日：2015-02-03

申请号：US14082448

申请日：2013-11-18

Applicant: Nalco Company

Inventor： Amy M. Tseng ,  Brian V. Jenkins ,  Robert Mack

IPC: G01N21/75

CPC classification number: G01N31/221 ,  B81C1/00531 ,  B81C2201/0132 ,  B81C2201/0142 ,  C09K13/00 ,  G01N21/272 ,  G01N21/80 ,  G01N35/085 ,  G01N2021/8411 ,  G01N2021/8557 ,  H01L21/67063 ,  H01L22/12 ,  Y10T436/153333

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract translation: 本发明涉及用于鉴定缓冲氧化物蚀刻组合物中氢氟酸的量的方法和组合物。 在缓冲氧化物蚀刻组合物中，非常难以测量氢氟酸的量，因为其具有不同的平衡，并且它是有毒的，因此难以处理和取样。 然而，当用于制造微芯片时，不正确量的氢氟酸会破坏这些芯片。 当与添加的显色剂接触时，本发明利用光谱测量氢氟酸的独特方法，以获得准确，立即和安全的精确测量。

公开(公告)号：US20140315320A1

公开(公告)日：2014-10-23

申请号：US14322009

申请日：2014-07-02

Applicant: Nalco Company

Inventor： Amy M. Tseng ,  Brian V. Jenkins ,  Robert M. Mack

IPC: G01N31/22

CPC classification number: G01N31/221 ,  B81C1/00531 ,  B81C2201/0132 ,  B81C2201/0142 ,  C09K13/00 ,  G01N21/272 ,  G01N21/80 ,  G01N35/085 ,  G01N2021/8411 ,  G01N2021/8557 ,  H01L21/67063 ,  H01L22/12 ,  Y10T436/153333

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract translation: 本发明涉及用于鉴定缓冲氧化物蚀刻组合物中氢氟酸的量的方法和组合物。 在缓冲氧化物蚀刻组合物中，非常难以测量氢氟酸的量，因为其具有不同的平衡，并且它是有毒的，因此难以处理和取样。 然而，当用于制造微芯片时，不正确量的氢氟酸会破坏这些芯片。 当与添加的显色剂接触时，本发明利用光谱测量氢氟酸的独特方法，以获得准确，立即和安全的精确测量。