公开(公告)号：US20060292354A1

公开(公告)日：2006-12-28

申请号：US11454412

申请日：2006-06-16

Applicant: Takuya Miyashita ,  Masafumi Okada ,  Kenji Matsumoto

Inventor： Takuya Miyashita ,  Masafumi Okada ,  Kenji Matsumoto

IPC: B32B3/00

CPC classification number: H05K3/282 ,  H05K3/325 ,  H05K2201/0162 ,  H05K2201/0179 ,  Y10T428/24917 ,  Y10T428/31681

Abstract: In a wiring substrate having a metal wiring pattern that is formed on a substrate and includes a contact portion for providing connection to an external element, an organic thin film containing silane is formed to cover the metal wiring pattern and the contact portion is electrically connected to the external element through the organic thing film. Unlike conventional wiring substrates in which a contact portion is uncovered by ripping open or cutting away a protective resin film formed on the contact portion, the wiring substrate can be electrically connected with an external element having a low contact pressure, for example.

Abstract translation: 在具有形成在基板上并且包括用于提供与外部元件的连接的接触部分的金属布线图案的布线基板中，形成含有硅烷的有机薄膜以覆盖金属布线图案，并且该接触部分电连接到 外部元素通过有机物膜。 与通过撕开或切除形成在接触部分上的保护树脂膜不接触接触部分的传统布线基板不同，布线基板可以例如与具有低接触压力的外部元件电连接。

公开(公告)号：US07138068B2

公开(公告)日：2006-11-21

申请号：US11084938

申请日：2005-03-21

Applicant: Gregory J. Dunn ,  Robert T. Croswell ,  Jaroslaw A. Magera ,  Jovica Savic ,  Aroon V. Tungare

Inventor： Gregory J. Dunn ,  Robert T. Croswell ,  Jaroslaw A. Magera ,  Jovica Savic ,  Aroon V. Tungare

IPC: H01L21/302

CPC classification number: C23F1/40 ,  C23F1/02 ,  C23F1/32 ,  C23F1/34 ,  H05K1/162 ,  H05K3/0044 ,  H05K3/025 ,  H05K3/06 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/025 ,  H05K2203/0746

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

公开(公告)号：US07118984B2

公开(公告)日：2006-10-10

申请号：US10368132

申请日：2003-02-14

Applicant: Kazuyoshi Honda ,  Noriyasu Echigo ,  Masaru Odagiri ,  Takanori Sugimoto

Inventor： Kazuyoshi Honda ,  Noriyasu Echigo ,  Masaru Odagiri ,  Takanori Sugimoto

IPC: H01L21/20

CPC classification number: H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0289 ,  H05K1/141 ,  H05K1/162 ,  H05K3/0026 ,  H05K3/403 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/049 ,  H05K2201/09236 ,  H05K2201/10734

Abstract: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed. An electronic component (10) configured in this manner is mounted on a wiring board, and a semiconductor chip can be mounted thereon. Along with connecting the semiconductor chip to the wiring board via the penetrating electrode (6), the semiconductor chip or the wiring board is connected to the lead electrodes (4, 5). In this manner, while suppressing the size increase of a mounted area, the capacitor or the like can be arranged near the semiconductor chip. Thus, the semiconductor chip is driven with high frequency more easily.

Abstract translation: 电极层（1,2）布置在相互面对的介质层（3）的两侧，以构成电容器。 在电极层（1,2）中形成引线电极（4,5）。 形成与电极层（1,2）绝缘的穿透电极（6）。 以这种方式配置的电子部件（10）安装在布线板上，并且可以在其上安装半导体芯片。 通过穿透电极（6）将半导体芯片与布线板连接，半导体芯片或布线基板与引线电极（4,5）连接。 以这种方式，在抑制安装区域的尺寸增加的同时，电容器等可以布置在半导体芯片附近。 因此，更容易地以高频率驱动半导体芯片。

公开(公告)号：US20060057420A1

公开(公告)日：2006-03-16

申请号：US10532717

申请日：2003-10-29

Applicant: Toshiko Yokota ,  Tetsuhiro Matsunaga ,  Susumu Takahashi ,  Hideaki Matsushima ,  Takuya Yamamoto ,  Makoto Dobashi

Inventor： Toshiko Yokota ,  Tetsuhiro Matsunaga ,  Susumu Takahashi ,  Hideaki Matsushima ,  Takuya Yamamoto ,  Makoto Dobashi

IPC: C23C14/00 ,  G01K5/66 ,  B32B15/20

CPC classification number: H01G4/33 ,  H05K1/162 ,  H05K2201/0154 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0355 ,  Y10T428/12514 ,  Y10T428/12903 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: To provide a dielectric-layer-provided copper foil or the like for extremely improving the product yield while making the most use of the increase effect of an electric capacity of a thin dielectric layer using the sputtering vapor deposition method. In the case of dielectric-layer-provided copper foils respectively having a dielectric layer on one side of a copper foil, the dielectric layer 6 is an inorganic-oxide sputter film having a thickness of 1.0 μm or less and formed on the one side of the copper foil in accordance with the sputtering vapor deposition method and the dielectric-layer-provided copper foils for respectively forming a capacitor layer, characterized in that a pit-like defective portion generated on the inorganic-oxide sputter film is sealed by polyimide resin are used.

Abstract translation: 提供一种提供介电层的铜箔等，以极大地提高产品产率，同时利用溅射气相沉积法最大限度地利用薄介电层的电容的增加效果。

公开(公告)号：US06998696B2

公开(公告)日：2006-02-14

申请号：US10686116

申请日：2003-10-15

Applicant: Michael D. Casper ,  William B. Mraz

Inventor： Michael D. Casper ,  William B. Mraz

IPC: H01L29/00

CPC classification number: H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L25/16 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19011 ,  H01Q21/061 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/002 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H01L2924/00

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract translation: 公开了用于在各种薄膜混合基板表面（0501）上制造高可靠性电容器（1011），电感器（1012）和多层互连（1013）（包括电阻器（1014））的系统和方法。 所公开的方法首先采用在衬底（0501）上沉积和图案化的薄金属层（0502）。 该薄图案层（0502）用于为上电极组件之间的电容器结构（0603）和互连（0604）提供两个下电极。 接下来，在薄的图案化层（0502）上沉积电介质层（0705），并且对电介质层（0705）进行图案化以将薄的图案化层的接触孔（0806）打开。 然后将上电极层（0907,0908,1009,1010）沉积并图案化在电介质（0705）的顶部。

公开(公告)号：US06974547B1

公开(公告)日：2005-12-13

申请号：US09711234

申请日：2000-11-13

Applicant: Naoki Kohara ,  Taisuke Sawada ,  Masatoshi Kitagawa

Inventor： Naoki Kohara ,  Taisuke Sawada ,  Masatoshi Kitagawa

IPC: H01G4/30 ,  H01G4/08 ,  H05K1/00 ,  H05K1/16 ,  H05K3/38 ,  H01L21/302 ,  C23F1/00

CPC classification number: H05K1/162 ,  H01G4/08 ,  H05K1/0393 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763

Abstract: According to a flexible thin film capacitor of the present invention, an adhesive film is formed on a substrate composed of at least one selected from the group consisting of an organic polymer and a metal foil, and an inorganic high dielectric film and metal electrode films are formed thereon. A metal oxide adhesive film can be used as the adhesive film. The adhesive film is formed in contact with the inorganic high dielectric film and at least one of the metal electrode films.

Abstract translation: 根据本发明的柔性薄膜电容器，在由选自有机聚合物和金属箔中的至少一种构成的基板上形成粘合膜，并且无机高介电膜和金属电极膜是 形成在其上。 可以使用金属氧化物粘合膜作为粘合膜。 该粘合膜形成为与无机高介电膜和至少一个金属电极膜接触。

公开(公告)号：US20050230146A1

公开(公告)日：2005-10-20

申请号：US11101163

申请日：2005-04-07

Applicant: Hideki Koyama

Inventor： Hideki Koyama

IPC: H01L23/498 ,  H01P3/08 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01P3/088 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/115 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10674

Abstract: A multilayer printed board comprising a plurality of capacitive coupling layers (6) each consisting of a dielectric layer (4) and a power supply layer (3) and a ground layer (5) facing each other while sandwiching the dielectric layer (4), first vias (7) connecting between the power supply layers (3) included in the plurality of capacitive coupling layers (6), and second vias (8) connecting between the ground layers (5) included in the plurality of capacitive coupling layers (6).

Abstract translation: 一种多层印刷电路板，包括多个电容耦合层（6），每个电容耦合层由电介质层（4）和电源层（3）和接地层（5）组成，同时夹着电介质层（4）， 连接在多个电容耦合层（6）中的电源层（3）之间的第一通孔（7）和连接在多个电容耦合层（6）中包括的接地层（5）之间的第二通孔（8） ）。

公开(公告)号：US06912113B2

公开(公告)日：2005-06-28

申请号：US10801324

申请日：2004-03-16

Applicant: Prabhat Kumar ,  Henning Uhlenhut

Inventor： Prabhat Kumar ,  Henning Uhlenhut

IPC: H01G4/33 ,  H01G4/10 ,  H01G4/38 ,  H01G9/00 ,  H01G9/15 ,  H05K1/16 ,  H01G4/30

CPC classification number: H01G9/15 ,  H01G4/10 ,  H01G11/48 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0329 ,  H05K2201/09763 ,  Y02E60/13

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film comprising an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film comprising an electrically conductive polymer located on the pentoxide layer.

Abstract translation: 本发明涉及一种薄膜电容器，其包含（a）基底，（b）第一聚合物膜，其包含位于基底上的导电聚合物，（c）五氧化物层，其选自五氧化二钽或五氧化二铌 ，及其混合物，（d）包含位于五氧化物层上的导电聚合物的第二聚合物膜。

公开(公告)号：US20050111162A1

公开(公告)日：2005-05-26

申请号：US10974789

申请日：2004-10-28

Applicant: Tetsuya Osaka ,  Ichiro Koiwa ,  Akira Hashimoto ,  Yoshimi Sato

Inventor： Tetsuya Osaka ,  Ichiro Koiwa ,  Akira Hashimoto ,  Yoshimi Sato

IPC: H01G4/12 ,  H01G2/00 ,  H01G4/008 ,  H01G4/06 ,  H01G4/30 ,  H01G4/33 ,  H01G13/00 ,  H01G13/06 ,  H01L21/822 ,  H01L27/04 ,  H05K1/16 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01G4/33 ,  H01G4/008 ,  H01G4/1227 ,  H01G13/006 ,  H05K1/162 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2203/016 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: A capacitor capable of being incorporated into a packaging substrate, characterized in that the capacitor comprises a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

Abstract translation: 一种能够结合到封装基板中的电容器，其特征在于，电容器包括高介电常数层，以及从上侧和下侧夹着高介电常数层的上电极层和下电极层 侧。 还提供了包含该电容器的封装基板及其制造方法。

公开(公告)号：US20050088783A1

公开(公告)日：2005-04-28

申请号：US10991900

申请日：2004-11-17

Applicant: Lin Zhou

Inventor： Lin Zhou

IPC: G11B5/48 ,  H05K1/02 ,  H05K1/05 ,  H05K3/00 ,  H05K3/04 ,  G11B5/55

CPC classification number: G11B5/187 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0221 ,  H05K1/056 ,  H05K3/0041 ,  H05K3/048 ,  H05K2201/0179 ,  H05K2201/09809 ,  H05K2203/0733 ,  Y10T29/49025 ,  Y10T29/49027 ,  Y10T29/49032 ,  Y10T29/49155 ,  Y10T29/49194

Abstract: An assembly includes a suspension, a magnetic head assembly, first and second write wires and first and second read wires wherein the magnetic head assembly includes a write head and a read head with the first and second write wires connected to the write head and the first and second read wires connected to the read head and wherein the first and second insulative sheaths are disposed about the first and second read wires and first and second conductive sheaths are disposed about the first and second insulative sheaths. In another aspect of the invention, third and fourth insulative sheaths are disposed about the first and second write wires and third and fourth conductive sheaths are disposed about the third and fourth insulative sheaths.

Abstract translation: 组件包括悬架，磁头组件，第一和第二写入线以及第一和第二读取线，其中磁头组件包括写入头和读取头，其中第一和第二写入线连接到写入头，第一和第二读取线 以及连接到读取头的第二读取线，并且其中第一和第二绝缘护套围绕第一和第二读取线设置，并且第一和第二导电护套围绕第一和第二绝缘护套设置。 在本发明的另一方面，第三和第四绝缘护套围绕第一和第二写入线布置，第三和第四导电护套围绕第三和第四绝缘护套设置。