Abstract:
A chip board package structure includes a circuit board part, a chip board part and a solder used to solder the circuit board part and the chip board part. A chip on the chip board part is connected to an electrical circuit by wiring or soldering. A surface treatment metal layer includes at least nickel, palladium and gold formed on part of the surface of the circuit layer on the chip board. A copper-tin intermetallic compound is formed on joints of the second solder and the surface treatment metal layer, and the other part of the circuit layer is directly connected to the solder to form the copper-tin intermetallic compound. In addition to the lower package cost, with the shape feature of the copper-tin intermetallic compound, it is possible to increase the contact area with the solder, thereby improving the reliability of the soldering process and the yield.
Abstract:
A conductive element includes a base having a first wavy surface, a second wavy surface, and a third wavy surface, a first layer provided on the first wavy surface, and a second layer provided on the second wavy surface. The first layer has a multilayer structure including two or more stacked sublayers, the second layer has a single-layer or multilayer structure including part of the sublayers constituting the first layer, and the first and second layers form a conductive pattern portion. The first, second, and third wavy surfaces satisfy the following relationship: 0≦(Am1/λm1)
Abstract:
A conducting film or device electrode includes a substrate and two transparent or semitransparent conductive layers separated by a transparent or semitransparent intervening layer. The intervening layer includes electrically conductive pathways between the first and second conductive layers to help reduce interfacial reflections occurring between particular layers in devices incorporating the conducting film or electrode.
Abstract:
A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. A covering layer is formed on the surface passivation layer, and the covering layer covers the surface passivation layer.
Abstract:
A multi-layer micro-wire structure includes a substrate having a surface. A plurality of micro-channels is formed in the substrate. A first material composition is located in a first layer only in each micro-channel and not on the substrate surface. A second material composition different from the first material composition is located in a second layer different from the first layer only in each micro-channel and not on the substrate surface. The first material composition in the first layer and the second material composition in the second layer form an electrically conductive multi-layer micro-wire in each micro-channel.
Abstract:
The present invention relates to an etching solution for copper or a compound comprised mainly of copper, wherein the etching solution contains (A) a maleic acid ion source and (B) a copper ion source, and an etching method using the etching solution.
Abstract:
Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.
Abstract:
There are provided a wiring board in which plating layers constituting wiring patterns are formed to have uniform thicknesses, and a method of manufacturing the wiring board. The wiring board includes an insulating layer; and wiring patterns formed on the insulating layer, wherein at least one of the wiring patterns is formed by stacking two or more plating layers.
Abstract:
Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the copper foil comprises a nickel or nickel alloy layer with a lower etching rate than copper formed on an etching side of the rolled copper foil or electrolytic copper foil, and a heat resistance layer composed of zinc or zinc alloy or its oxide formed on the nickel or nickel alloy layer. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel or nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKE”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width.
Abstract:
A method of electroplating and depositing metal includes: providing an insulation substrate formed with conductive through holes; forming a first conductive layer on a first surface of the insulation substrate and forming a resist layer on a first portion of the first conductive layer, leaving a second portion of the first conductive layer uncovered by the resist layer as a to-be-plated area; disposing the insulation substrate in a first electroplating solution and depositing a first metal layer on the to-be-plated area; removing the resist layer and the portion of the first conductive layer; forming a second conductive layer on a second surface of the insulation substrate; forming a mask layer on the second conductive layer; disposing the insulation substrate in a second electroplating solution and depositing a second metal layer on the first metal layer of the to-be-plated area; and removing the mask layer and the second conductive layer.