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    CHIP BOARD PACKAGE STRUCTURE
    61.
    发明申请
    CHIP BOARD PACKAGE STRUCTURE 审中-公开
    芯板包装结构

    公开(公告)号：US20150041183A1

    公开(公告)日：2015-02-12

    申请号：US13960082

    申请日：2013-08-06

    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

    Inventor： Jun-Chung Hsu ,  Yu-Hui Wu ,  Huei-Cheng Hong

    IPC: H05K1/11 ,  H05K1/02

    CPC classification number: H05K1/09 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/111 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/0338 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A chip board package structure includes a circuit board part, a chip board part and a solder used to solder the circuit board part and the chip board part. A chip on the chip board part is connected to an electrical circuit by wiring or soldering. A surface treatment metal layer includes at least nickel, palladium and gold formed on part of the surface of the circuit layer on the chip board. A copper-tin intermetallic compound is formed on joints of the second solder and the surface treatment metal layer, and the other part of the circuit layer is directly connected to the solder to form the copper-tin intermetallic compound. In addition to the lower package cost, with the shape feature of the copper-tin intermetallic compound, it is possible to increase the contact area with the solder, thereby improving the reliability of the soldering process and the yield.

    Abstract translation: 芯片组封装结构包括电路板部分，芯片板部分和用于焊接电路板部分和芯片板部分的焊料。 芯片部分的芯片通过布线或焊接连接到电路。 表面处理金属层至少包括在芯片板上的电路层表面的一部分上形成的镍，钯和金。 在第二焊料和表面处理金属层的接合部上形成铜锡金属间化合物，电路层的另一部分与焊锡直接连接，形成铜锡金属间化合物。 除了较低的封装成本之外，通过铜 - 锡金属间化合物的形状特征，可以增加与焊料的接触面积，从而提高焊接工艺的可靠性和产率。

    Conductive element and method for producing the same, wiring element, information input device, display device, electronic apparatus, and master
    62.
    发明授权
    Conductive element and method for producing the same, wiring element, information input device, display device, electronic apparatus, and master 有权
    导电元件及其制造方法，布线元件，信息输入装置，显示装置，电子设备和主机

    公开(公告)号：US08872039B2

    公开(公告)日：2014-10-28

    申请号：US13413390

    申请日：2012-03-06

    Applicant: Shunichi Kajiya ,  Kazuya Hayashibe

    Inventor： Shunichi Kajiya ,  Kazuya Hayashibe

    IPC: H05K1/03 ,  G06F3/041 ,  H05K3/06 ,  G06F3/044 ,  G06F3/047 ,  G02F1/167

    CPC classification number: G06F3/0412 ,  G02F2001/1676 ,  G06F3/044 ,  G06F3/047 ,  H05K3/06 ,  H05K2201/0338 ,  Y10S977/742 ,  Y10S977/773 ,  Y10S977/932

    Abstract: A conductive element includes a base having a first wavy surface, a second wavy surface, and a third wavy surface, a first layer provided on the first wavy surface, and a second layer provided on the second wavy surface. The first layer has a multilayer structure including two or more stacked sublayers, the second layer has a single-layer or multilayer structure including part of the sublayers constituting the first layer, and the first and second layers form a conductive pattern portion. The first, second, and third wavy surfaces satisfy the following relationship: 0≦(Am1/λm1)

    Abstract translation: 导电元件包括​​具有第一波状表面，第二波浪表面和第三波浪表面的基底，设置在第一波浪表面上的第一层和设置在第二波状表面上的第二层。 第一层具有包括两个或更多层叠的子层的多层结构，第二层具有包括构成第一层的子层的一部分的单层或多层结构，第一层和第二层形成导电图案部分。 第一，第二和第三波纹表面满足以下关系：0＆nlE;（Am1 /λm1）<（Am2 /λm2）<（Am3 /λm3）＆nlE; 1.8（Am1：第一波形表面的平均振幅，Am2： 第二波形表面的Am3：第三波形表面的平均振幅，λm1：第一波形表面的平均波长，λm2：第二波形表面的平均波长，λm3：第三波浪表面的平均波长）。

    MANUFACTURING METHOD OF CIRCUIT STRUCTURE
    64.
    发明申请
    MANUFACTURING METHOD OF CIRCUIT STRUCTURE 审中-公开
    电路结构的制造方法

    公开(公告)号：US20140295353A1

    公开(公告)日：2014-10-02

    申请号：US14304988

    申请日：2014-06-16

    Applicant: Ching-Sheng Chen

    Inventor： Ching-Sheng Chen

    IPC: H05K3/28

    CPC classification number: H05K3/28 ,  H05K3/062 ,  H05K2201/0338

    Abstract: A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. A covering layer is formed on the surface passivation layer, and the covering layer covers the surface passivation layer.

    Abstract translation: 提供一种电路结构的制造方法。 提供具有上表面的金属层。 在金属层上形成表面钝化层。 表面钝化层暴露金属层的上表面的一部分，并且金属层的材料不同于表面钝化层的材料。 在表面钝化层上形成覆盖层，覆盖层覆盖表面钝化层。

    CIRCUIT BOARD HAVING TIE BAR BURIED THEREIN AND METHOD OF FABRICATING THE SAME
    67.
    发明申请
    CIRCUIT BOARD HAVING TIE BAR BURIED THEREIN AND METHOD OF FABRICATING THE SAME 有权
    电路板及其制造方法

    公开(公告)号：US20140131085A1

    公开(公告)日：2014-05-15

    申请号：US13674919

    申请日：2012-11-12

    Applicant: Hsin-Mao Huang ,  Chun-Huang Yu

    Inventor： Hsin-Mao Huang ,  Chun-Huang Yu

    IPC: H05K1/11 ,  H05K3/10

    CPC classification number: H05K3/242 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/113 ,  H05K1/117 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2203/0228

    Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.

    Abstract translation: 提供一种具有埋入其中的连接杆的电路板。 电路板包括电介质叠层，至少第一连接条，至少第一金指和至少第一微孔。 电介质堆叠包括第一电介质层和第二电介质层。 第一电介质层位于第二电介质层上。 电介质堆叠包括有线区域和金指区域。 第一连杆被埋在第一介电层和第二介电层之间的金指区域中。 至少第一金手指位于第一介电层上的金指区域中。 第一微孔位于第一电介质层中的金指区域中，并且将第一金手指电连接到第一连接杆。

    Method of Electroplating and Depositing Metal
    70.
    发明申请
    Method of Electroplating and Depositing Metal 有权
    电镀和沉积金属的方法

    公开(公告)号：US20140001051A1

    公开(公告)日：2014-01-02

    申请号：US13623480

    申请日：2012-09-20

    Applicant: Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Hung Ho

    Inventor： Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Hung Ho

    IPC: C25D5/02 ,  C25D5/10

    CPC classification number: H05K3/02 ,  H05K3/108 ,  H05K3/242 ,  H05K3/4053 ,  H05K3/42 ,  H05K2201/0338 ,  H05K2201/0347

    Abstract: A method of electroplating and depositing metal includes: providing an insulation substrate formed with conductive through holes; forming a first conductive layer on a first surface of the insulation substrate and forming a resist layer on a first portion of the first conductive layer, leaving a second portion of the first conductive layer uncovered by the resist layer as a to-be-plated area; disposing the insulation substrate in a first electroplating solution and depositing a first metal layer on the to-be-plated area; removing the resist layer and the portion of the first conductive layer; forming a second conductive layer on a second surface of the insulation substrate; forming a mask layer on the second conductive layer; disposing the insulation substrate in a second electroplating solution and depositing a second metal layer on the first metal layer of the to-be-plated area; and removing the mask layer and the second conductive layer.

    Abstract translation: 一种电镀和沉积金属的方法包括：提供形成有导电通孔的绝缘基板; 在所述绝缘基板的第一表面上形成第一导电层，并在所述第一导电层的第一部分上形成抗蚀剂层，留下未被所述抗蚀剂层覆盖的所述第一导电层的第二部分作为被镀覆区域 ; 将所述绝缘基板设置在第一电镀溶液中并在所述被镀区域上沉积第一金属层; 去除所述抗蚀剂层和所述第一导电层的所述部分; 在所述绝缘基板的第二表面上形成第二导电层; 在所述第二导电层上形成掩模层; 将所述绝缘基板设置在第二电镀液中，并在所述被镀区域的所述第一金属层上沉积第二金属层; 以及去除掩模层和第二导电层。

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