公开(公告)号：US20060030080A1

公开(公告)日：2006-02-09

申请号：US10913868

申请日：2004-08-06

Applicant: Paul Hsueh ,  Jim Ni ,  Sun-Teck See ,  Kuang-Yu Wang

Inventor： Paul Hsueh ,  Jim Ni ,  Sun-Teck See ,  Kuang-Yu Wang

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: G11C5/04 ,  G11C2029/4402 ,  H01L23/5388 ,  H01L25/50 ,  H01L2924/0002 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/10053 ,  H05K2201/10446 ,  H05K2203/1316 ,  H01L2924/00

Abstract: A removable Flash integrated memory module card has a plastic shell and an integral Flash memory module. On the backside of the card, there are exposed contact pads. When the card is inserted into a card-hosting device, the card can communicate with the device through the exposed pads. The manufacturing method includes manufacturing of the memory module and utilizing plastic molding techniques for making the card outer body. The method involves preparing the substrate, mounting the components, testing the module, preparing the molding device, and molding the card body.

Abstract translation: 可拆卸的Flash集成内存模块卡具有塑料外壳和集成闪存模块。 在卡的背面，有暴露的接触垫。 当卡插入卡主机设备时，卡可以通过暴露的焊盘与设备通信。 该制造方法包括制造存储器模块并利用塑料模制技术制造卡外壳。 该方法包括准备基板，安装部件，测试模块，准备模制装置和模制卡体。

公开(公告)号：US20060027918A1

公开(公告)日：2006-02-09

申请号：US10911585

申请日：2004-08-05

Applicant: Kai-Chiang Wu ,  Shaw-Wei Chen

Inventor： Kai-Chiang Wu ,  Shaw-Wei Chen

IPC: H01L23/34

CPC classification number: H01L23/585 ,  H01L24/10 ,  H01L2924/0102 ,  H01L2924/01079 ,  H05K3/0052 ,  H05K3/242 ,  H05K2201/09036 ,  H05K2201/0909

Abstract: An electroplated wire layout for package sawing comprises a substrate with a plurality of chip arrays disposed thereon. A kerf having two scribe lines is disposed between every two chip arrays. Several solder ball pads corresponding to the chip arrays are disposed on a back surface of the substrate. Each solder ball pad has a solder ball electroplated wire extended into a kerf. There is also a kerf electroplated wire disposed in each kerf and above the scribe lines of the kerf in a zigzag way. The kerf electroplated wire is connected with the solder ball pad electroplated wires to achieve electric connection. By changing the shape of the kerf electroplated wire, the kerf electroplated wire can be easily cut off to enhance the yield and reliability and also lower the cost.

Abstract translation: 用于包装锯切的电镀线布局包括其上布置有多个芯片阵列的基板。 在每两个芯片阵列之间设置具有两个划痕线的切口。 对应于芯片阵列的几个焊球垫设置在基板的背面上。 每个焊球垫具有延伸到切口中的焊球电镀丝。 还有一个切口电镀线，以锯齿形的方式设置在每个切口上并且在切口的划线之上。 切割电镀线与焊球电镀线连接，实现电连接。 通过改变切口电镀线的形状，切割电镀线可以容易地切断，以提高产量和可靠性，并降低成本。

公开(公告)号：US06951707B2

公开(公告)日：2005-10-04

申请号：US10184387

申请日：2002-06-27

Applicant: Alan E. Wang ,  Kevin C. Olson

Inventor： Alan E. Wang ,  Kevin C. Olson

IPC: H05K1/05 ,  H05K3/00 ,  H05K3/06 ,  H05K3/44 ,  H05K3/46 ,  G03F7/00

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract translation: 提供了一种用于创建电路组件的通孔的方法，包括以下步骤：（a）将可固化涂料组合物施加到基底上，其中一些或全部导电，以在其上形成未固化的涂层; （b）在未固化的涂层上涂覆抗蚀剂; （c）在预定位置对抗蚀剂进行成像; （d）显影抗蚀剂以暴露未固化涂层的预定区域; （e）去除未固化涂层的暴露区域; 和（f）将步骤（e）的涂布基材加热到足以固化涂层的温度和时间。还公开了一种制造电路组件的方法。

公开(公告)号：US20050124196A1

公开(公告)日：2005-06-09

申请号：US10987480

申请日：2004-11-11

Applicant: Kevin Olson ,  Alan Wang ,  Peter Elenius ,  Thomas Goodman

Inventor： Kevin Olson ,  Alan Wang ,  Peter Elenius ,  Thomas Goodman

IPC: H05K1/05 ,  H05K1/02 ,  H05K3/00 ,  H05K3/44 ,  H05K3/46 ,  H01R13/15

CPC classification number: H05K3/002 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135

Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Abstract translation: 多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片的另一表面的绝缘底层和覆盖 导电片的边缘。 绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。 无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。

公开(公告)号：US06844504B2

公开(公告)日：2005-01-18

申请号：US10227768

申请日：2002-08-26

Applicant: Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

Inventor： Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

IPC: H05K1/05 ,  H05K3/00 ,  H05K3/06 ,  H05K3/44 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Abstract translation: 根据本发明的电路板层2包括夹在绝缘顶层10和绝缘底层14之间的导电片4.顶层10和底层14以及导电片4限定电路板层2，其具有 包括导电片4的边缘20的边缘。绝缘边缘层18几乎覆盖导电片4的所有边缘20。

公开(公告)号：US20050008824A1

公开(公告)日：2005-01-13

申请号：US10476155

申请日：2003-01-24

Applicant: Hiromichi Kawakami ,  Yoshifumi Saito

Inventor： Hiromichi Kawakami ,  Yoshifumi Saito

IPC: C04B35/64 ,  B28B11/00 ,  B28B11/12 ,  B28B11/24 ,  H01L21/48 ,  H01L23/12 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  B32B9/00

CPC classification number: H05K3/0052 ,  B28B11/243 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/4629 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2203/308 ,  Y10T428/2457 ,  Y10T428/24926 ,  H01L2924/00

Abstract: To produce a green composite laminate 11, a green multilayer collective substrate 13 containing low-temperature sinterable glass ceramic powder as a main ingredient is disposed between first and second shrinkage-restraining layers 14a and 14b containing alumina powder as a main ingredient. Grooves 16 are formed on one main surface 11a of the green composite laminate 11 such as to pass through the first shrinkage-restraining layer 14a and the green multilayer collective substrate 13 and reach the second shrinkage-restraining layer 14b, but not to reach the other main surface 11b of the green composite laminate 11. The green composite laminate 11 provided with the grooves 16 is sintered under conditions where the low-temperature sinterable glass ceramic powder is sintered and the green first and second shrinkage-restraining layers 14a and 14b are removed to prepare a plurality of ceramic multilayer substrates. This manufacturing method offers ceramic multilayer substrates with a high dimensional accuracy and substantially prevents defective divisions when a multilayer collective substrate is split into a plurality of ceramic multilayer substrates.

Abstract translation: 为了制造绿色复合层叠体11，以含有低温烧结玻璃陶瓷粉末为主要成分的绿色多层集合基板13配置在以氧化铝粉末为主要成分的第一和第二收缩抑制层14a，14b之间。 沟槽16形成在绿色复合层压体11的一个主表面11a上，以通过第一收缩抑制层14a和绿色多层收集基板13到达第二收缩抑制层14b但不到达另一个 绿色复合层叠体11的主表面11b。在烧结低温可烧结玻璃陶瓷粉末并除去绿色第一和第二收缩抑制层14a和14b的条件下烧结设置有槽16的生坯复合层叠体11 以制备多个陶瓷多层基板。 该制造方法提供具有高尺寸精度的陶瓷多层基板，并且当将多层集合基板分割成多个陶瓷多层基板时，基本上防止有缺陷的划分。

公开(公告)号：US20040195010A1

公开(公告)日：2004-10-07

申请号：US10787277

申请日：2004-02-26

Applicant: PACE MICRO TECHNOLOGY PLC

Inventor： Vic Fielding

IPC: G01G023/02

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K1/0275 ,  H05K3/0052 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/0999 ,  H05K2203/167

Abstract: A printed circuit board (PCB) is provided for use with electrical apparatus. The PCB has a body with a surface provided for the location of electrical components thereon and electrically conductive tracks are provided for electrically connecting the component in a required arrangement. A portion of the PCB body has a test port thereon for allowing testing of functions of the PCB, electrical conductive tracks and/or electrical components. The testing portion of the PCB body provided with the test ports is detachably attached to the PCB body to allow removal therefrom.

Abstract translation: 提供印刷电路板（PCB）以用于电气设备。 PCB具有设置在其上的电气部件的位置的表面的主体，并且提供导电轨道用于以所需布置电连接部件。 PCB体的一部分具有测试端口，用于测试PCB，导电轨迹和/或电气部件的功能。 设置有测试端口的PCB主体的测试部分可拆卸地附接到PCB主体以允许从其移除。

公开(公告)号：US06698638B2

公开(公告)日：2004-03-02

申请号：US10150815

申请日：2002-05-20

Applicant: Gary E. Stanek

Inventor： Gary E. Stanek

IPC: B26F300

CPC classification number: B26F3/002 ,  B26D7/18 ,  B26F2210/08 ,  H05K3/0052 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2203/302 ,  Y10T225/30 ,  Y10T225/325 ,  Y10T225/371

Abstract: A PCB scrap edge removal tool comprising scrap removal jaws formed of two matching opposing pieces of metal having cut-outs in a castellated fashion. The jaws have a gap between them for receiving a PCB work piece to be finished. Metal dowels for PCB positioning span the gap. A PCB is positioned in the gap and rocked back and forth to break off the scrap edge pieces. The cut-outs in the scrap removal jaws correspond to portions of the PCB edge that are not to be removed. These portions move freely in the cut-outs as the PCB is rocked back and forth.

Abstract translation: 一种PCB边缘去除工具，其包括由具有镂空方式​​的切口的两个匹配的相对的金属片形成的废料去除钳口。 夹爪之间有一个差距，用于接收待完成的PCB工件。 用于PCB定位的金属定位销跨越了间隙。 PCB被定位在间隙中并且前后摆动以分离边缘碎片。 废料去除爪中的切口对应于PCB边缘的不被去除的部分。 这些部分随着PCB前后摇动而在切口中自由移动。

公开(公告)号：US20040001325A1

公开(公告)日：2004-01-01

申请号：US10227768

申请日：2002-08-26

Inventor： Alan E. Wang ,  Kevin C. Olson ,  Thomas H. Di Stefano

IPC: H05K001/18

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Abstract translation: 根据本发明的电路板层2包括夹在绝缘顶层10和绝缘底层14之间的导电片4.顶层10和底层14以及导电片4限定电路板层2，其具有 包括导电片4的边缘20的边缘。绝缘边缘层18几乎覆盖导电片4的所有边缘20。

公开(公告)号：US06640435B2

公开(公告)日：2003-11-04

申请号：US09789370

申请日：2001-02-20

Applicant: Balu Balakrishnan

Inventor： Balu Balakrishnan

IPC: H05K302

CPC classification number: H05K3/225 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/0293 ,  H05K3/0047 ,  H05K3/005 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/10689 ,  H05K2203/0228 ,  H05K2203/171 ,  H05K2203/175 ,  Y10T29/49004 ,  Y10T29/49082 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49787 ,  Y10T29/49789 ,  Y10T29/4979 ,  Y10T29/49798 ,  Y10T29/5149 ,  Y10T29/515

Abstract: Electrical circuit trimming methods. In one aspect of the invention, a trimming method includes assembling one or more components of an electrical circuit onto a printed circuit board having one or more electrical connections coupled to the said one or more components. An electrical parameter of the electrical circuit is then trimmed. The trimming of the electrical parameter of the electrical circuit includes removing a portion of the printed circuit board to break the electrical connection on the printed circuit board. In another aspect of the invention, the trimming the electrical parameter of the electrical circuit includes electrical programming of the electrical circuit.