公开(公告)号：US20090038837A1

公开(公告)日：2009-02-12

申请号：US12078176

申请日：2008-03-27

Applicant: Shuhichi Okabe ,  Jin-Yong An ,  Seok-Kyu Lee ,  Soon-Oh Jung ,  Jong-Kuk Hong ,  Hae-Nam Seo

Inventor： Shuhichi Okabe ,  Jin-Yong An ,  Seok-Kyu Lee ,  Soon-Oh Jung ,  Jong-Kuk Hong ,  Hae-Nam Seo

IPC: H05K1/11 ,  B32B38/10

CPC classification number: H05K3/462 ,  H05K3/205 ,  H05K3/243 ,  H05K3/421 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096

Abstract: A multilayered printed circuit board is disclosed. A method of manufacturing the multilayered printed circuit board, which includes: forming a metal layer and a lower-circuit-forming pattern in order on a carrier, and forming a lower circuit by filling a conductive material in the lower-circuit-forming pattern; removing the lower-circuit-forming pattern, stacking an insulation resin, and forming at least one via hole connecting with the lower circuit; forming at least one inner circuit and at least one interlayer connector connecting the inner circuit with the lower circuit on the insulation resin, to form a pair of circuit parts; and aligning the pair of circuit parts, attaching the pair of circuit parts to each other, and removing the carrier and the metal layer, allows the forming of fine-lined circuits and provides a thin board, while preventing bending and warpage in the board.

Abstract translation: 公开了一种多层印刷电路板。 一种制造多层印刷电路板的方法，包括：在载体上依次形成金属层和下电路形成图案，并通过在下电路形成图案中填充导电材料形成下层电路; 去除下部电路形成图案，堆叠绝缘树脂，并形成与下部电路连接的至少一个通孔; 在所述绝缘树脂上形成至少一个内部电路和连接所述内部电路与所述下部电路的至少一个层间连接器，以形成一对电路部件; 并且将一对电路部件对准，将一对电路部件彼此连接，并且移除载体和金属层，允许形成精细的电路并提供薄板，同时防止板的弯曲和翘曲。

公开(公告)号：US07387917B2

公开(公告)日：2008-06-17

申请号：US11086625

申请日：2005-03-22

Applicant: Jae Min Choi ,  Young Hwan Shin

Inventor： Jae Min Choi ,  Young Hwan Shin

IPC: H01L21/00

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19043 ,  H05K1/113 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.

Abstract translation: 公开了一种球栅阵列（BGA）封装基板，其中引线接合焊盘和焊球焊盘形成在通孔上，使电路图案的设计和高密度电路图案具有高自由度，以及方法 的制造。

公开(公告)号：US20080029297A1

公开(公告)日：2008-02-07

申请号：US11882198

申请日：2007-07-31

Applicant: Junichi Nakamura

Inventor： Junichi Nakamura

IPC: H05K1/11

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09527 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring substrate includes a first insulation layer, a connection terminal, a second insulation layer, a via, and a wiring pattern. The connection terminal is disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer, and is electrically connected with a semiconductor chip. The second insulation layer is disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface. The via is disposed in the second insulation layer, and is electrically connected with the connection terminal. The via is separated from the connection terminal. The wiring pattern is disposed on the second main surface of the first insulation layer and electrically connects the connection terminal and the via.

Abstract translation: 布线基板包括第一绝缘层，连接端子，第二绝缘层，通孔和布线图案。 连接端子设置在第一绝缘层中，以从第一绝缘层的第一主表面露出，并与半导体芯片电连接。 第二绝缘层设置在位于与第一主表面相反一侧的第一绝缘层的第二主表面上。 通孔设置在第二绝缘层中，并与连接端子电连接。 通孔与连接端子分离。 布线图案设置在第一绝缘层的第二主表面上，并且电连接连接端子和通孔。

公开(公告)号：US07019404B2

公开(公告)日：2006-03-28

申请号：US10347602

申请日：2003-01-22

Applicant: Akio Rokugawa ,  Takahiro Iijima

Inventor： Akio Rokugawa ,  Takahiro Iijima

IPC: H01L29/40

CPC classification number: H01L23/49531 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/48 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H05K1/113 ,  H05K3/0061 ,  H05K3/205 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0133 ,  H05K2201/09527 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can be arranged on the first surface of the substrate body; and a plate member, a rigidity thereof being higher than that of the substrate body, attached to the second surface of the substrate body. A plurality of semiconductor elements can be mounted on the semiconductor element mounting surface defined on the first surface of the substrate body.

公开(公告)号：US20060042824A1

公开(公告)日：2006-03-02

申请号：US11260077

申请日：2005-10-27

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: H05K5/06

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

公开(公告)号：US06972382B2

公开(公告)日：2005-12-06

申请号：US10626242

申请日：2003-07-24

Applicant: James A. Zollo ,  Nitin B. Desai

Inventor： James A. Zollo ,  Nitin B. Desai

IPC: H05K3/46 ,  H05K1/11 ,  H01R12/04

CPC classification number: H05K3/4623 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2201/096 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A multilayer circuit board (50) includes a plurality of substrate cores (34 and 44), an adhesive/bonding layer (55) between at least two among the plurality of substrate cores, and a microvia (35 and 45) in each of at least two of the plurality of substrate cores. The microvia includes a conductive interconnection (39) between a top conductive surface and a bottom conductive surface of each of the plurality of substrate cores and the microvia in a first substrate core is arranged to be inverted relative to a microvia in a second substrate core. The multilayer circuit board can further include a plated through-hole (54) through the plurality of substrate cores and the adhesive/bonding layer such that at least two among the top conductive surfaces (32 or 46) and the bottom conductive surfaces (36 or 42) of the plurality of substrate cores are connected.

Abstract translation: 多层电路板（50）包括多个基板芯（34和44），多个基板芯中的至少两个之间的粘合/粘合层（55）和每个基板芯中的微孔（35和45） 多个基板芯中的至少两个。 微孔包括在多个基板芯的每个的顶部导电表面和底部导电表面之间的导电互连（39），并且第一基板芯中的微孔被布置成相对于第二基板芯中的微孔而相反。 多层电路板还可以包括通过多个衬底芯和粘合/粘合层的电镀通孔（54），使得顶部导电表面（32或46）和底部导电表面（36或36）中的至少两个 连接多个基板芯的42）。

公开(公告)号：US20050231889A1

公开(公告)日：2005-10-20

申请号：US11100827

申请日：2005-04-06

Applicant: Yoshiomi Tsuji

Inventor： Yoshiomi Tsuji

IPC: H01G2/00 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09718

Abstract: A capacitor-embedded substrate for reliably compensating for fluctuation of a power source voltage is provided. A decoupling capacitor is formed between an input side electrode layer and an output side electrode layer via interlayer insulating layers, the decoupling capacitor includes a ground layer, a power source layer, and a dielectric layer interposed therebetween. A plurality of power supply terminals used for power supply to a semiconductor device is formed by patterning the output side electrode layer and is connected to the power source layer via a capacitor via.

Abstract translation: 提供了用于可靠地补偿电源电压波动的电容器嵌入式基板。 在输入侧电极层和输出侧电极层之间经由层间绝缘层形成去耦电容器，去耦电容器包括接地层，电源层和介于其间的电介质层。 用于向半导体器件供电的多个电源端子通过对输出侧电极层进行构图而形成，并通过电容器通孔连接到电源层。

公开(公告)号：US06715204B1

公开(公告)日：2004-04-06

申请号：US09720953

申请日：2001-02-13

Applicant: Kiyotaka Tsukada ,  Masaru Takada ,  Kenji Chihara

Inventor： Kiyotaka Tsukada ,  Masaru Takada ,  Kenji Chihara

IPC: H05K302

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A printed circuit board and a method for manufacturing the same that facilitates the formation of an upper surface pattern and prevents a lower surface metal foil from being damaged when forming a blind via hole with a laser. A lower surface and an upper surface of an insulative substrate (5) are respectively coated with a lower surface metal foil (220) and an upper surface metal foil (210), the thickness of which is less than that of the lower surface metal foil (220). Next, an opening (213) is formed in the upper surface metal foil at a location corresponding to a blind via hole formation portion (35) of the insulative substrate. A blind via hole (3), the bottom of which is the lower surface metal foil, is formed by emitting a laser (8) against the blind via hole formation portion (35) through the opening (213). Then, a metal plating film (23) is applied to the wall of the blind via hole (3), and an upper surface pattern (21) and a lower surface pattern (22) are formed through etching.

Abstract translation: 一种印刷电路板及其制造方法，其有助于形成上表面图案，并且在用激光形成盲孔时防止下表面金属箔被损坏。 绝缘基板（5）的下表面和上表面分别涂覆有下表面金属箔（220）和上表面金属箔（210），其厚度小于下表面金属箔的厚度 （220）。 接着，在与上述绝缘性基板的盲通孔形成部（35）对应的位置，在上表面金属箔上形成有开口部（213）。 通过开口（213）向盲通孔形成部分（35）发射激光器（8），形成底部金属薄片的盲孔（3）。 然后，将金属镀膜（23）施加到盲孔（3）的壁上，通过蚀刻形成上表面图案（21）和下表面图案（22）。

公开(公告)号：US20030203170A1

公开(公告)日：2003-10-30

申请号：US10408588

申请日：2003-04-07

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: B32B003/00

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。

公开(公告)号：US20030138992A1

公开(公告)日：2003-07-24

申请号：US10347602

申请日：2003-01-22

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD

Inventor： Akio Rokugawa ,  Takahiro Iijima

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H05K003/36

CPC classification number: H01L23/49531 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/48 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H05K1/113 ,  H05K3/0061 ,  H05K3/205 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0133 ,  H05K2201/09527 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can be arranged on the first surface of the substrate body; and a plate member, a rigidity thereof being higher than that of the substrate body, attached to the second surface of the substrate body. A plurality of semiconductor elements can be mounted on the semiconductor element mounting surface defined on the first surface of the substrate body.

Abstract translation: 一种用于半导体器件的多层电路衬底包括具有第一表面和第二表面的多层电路衬底体，并且包括从第一表面到第二表面一个层叠在一起的多个导电图案层，使得多个 的半导体器件元件可以布置在基板主体的第一表面上; 以及板构件，其刚度高于基板主体的刚度，附着到基板主体的第二表面。 多个半导体元件可以安装在限定在基板主体的第一表面上的半导体元件安装面上。