公开(公告)号：US09955586B2

公开(公告)日：2018-04-24

申请号：US14800751

申请日：2015-07-16

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Ting-Ying Wu ,  Cheng-Lin Wu ,  Chin-Yuan Lo ,  Wen-Shan Wang

IPC: H05K7/10 ,  H05K3/34 ,  H01L23/498 ,  H01L23/50 ,  H05K7/00 ,  H05K7/12 ,  H05K1/02

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0215 ,  H05K1/0289 ,  H05K2201/10159 ,  H05K2201/10704 ,  H05K2201/10712 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

Abstract: A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.

公开(公告)号：US20160021745A1

公开(公告)日：2016-01-21

申请号：US14800751

申请日：2015-07-16

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： TING-YING WU ,  CHENG-LIN WU ,  CHIN-YUAN LO ,  WEN-SHAN WANG

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0215 ,  H05K1/0289 ,  H05K2201/10159 ,  H05K2201/10704 ,  H05K2201/10712 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

Abstract: A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.

Abstract translation: 提供了一种形成在印刷电路板上的球栅阵列（BGA）。 BGA包括第一焊球模块和第二焊球模块。 第一焊球模块包括多个第一焊球，其中第一焊球之一接地以屏蔽两个其它第一焊球，并且第一焊球中的一个浮动。 第二焊球模块包括多个第二焊球，其中两个第二焊球接地，并且两个接地的第二焊球中的一个通过形成在印刷电路板上的电镀通孔穿透印刷电路板，用于屏蔽两个 第一焊球之间的第一焊球。

公开(公告)号：US08546700B2

公开(公告)日：2013-10-01

申请号：US13042686

申请日：2011-03-08

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K1/16

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract translation: 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US20130000820A1

公开(公告)日：2013-01-03

申请号：US13610936

申请日：2012-09-12

Applicant: Motohiko SATO ,  Kazuhiro HAYASHI ,  Kenji MURAKAMI ,  Motonobu KURAHASHI ,  Yusuke KAIEDA ,  Jun OTSUKA ,  Manabu SATO

Inventor： Motohiko SATO ,  Kazuhiro HAYASHI ,  Kenji MURAKAMI ,  Motonobu KURAHASHI ,  Yusuke KAIEDA ,  Jun OTSUKA ,  Manabu SATO

IPC: H01G13/00 ,  B32B37/14

CPC classification number: H05K1/0231 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract translation: 一种电容器，其具有电容器，所述电容器包括：电容器主体，包括多个电介质层和设置在所述不同电介质层之间的内部电极层，其中所述电容器本体在所述电容器主体的至少一个侧面中， 从所述电容器主体的第一主面和位于与所述第一主面相反的一侧的第二主面中的至少一个在所述电容器本体的厚度方向上延伸的凹部。

公开(公告)号：US20120279770A1

公开(公告)日：2012-11-08

申请号：US13554315

申请日：2012-07-20

Applicant: Hiroyasu NAGATA

Inventor： Hiroyasu NAGATA

IPC: H05K1/18 ,  H05K3/30 ,  H05K1/03

CPC classification number: B32B37/025 ,  B32B2038/0092 ,  B32B2309/02 ,  B32B2309/105 ,  B32B2309/12 ,  B32B2457/08 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2518 ,  H05K1/0231 ,  H05K1/0269 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2201/10712 ,  H05K2203/166 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1052 ,  Y10T156/11 ,  Y10T156/1195

Abstract: A method for manufacturing printed wiring board including preparing an electronic component having first and second surfaces and electrode on the first surface, forming in an adhesive tape a mark, mounting based on the mark the component on the tape such that the second surface faces the adhesive of the tape, forming another mark on insulative substrate having first and second surfaces, forming in the substrate an opening larger than the component, mounting based on the marks the substrate on the tape such that the component is in the opening of the substrate, fixing the component to the substrate using resin, forming an insulation layer on the first surface of the substrate where the component is accommodated, removing the tape, forming in the layer an opening reaching the electrode, forming a conductive circuit on the layer, and forming in the opening of the layer a via connected to the electrode.

Abstract translation: 一种制造印刷线路板的方法，包括制备具有第一和第二表面的电子部件和在第一表面上的电极，在胶带上形成标记，基于将该部件标记在带上以使得第二表面面向粘合剂 的带，在具有第一和第二表面的绝缘基板上形成另一个标记，在基板上形成比部件大的开口，基于将基板标记在带上的安装，使得部件在基板的开口中，固定 使用树脂的基板上的部件，在容纳部件的基板的第一表面上形成绝缘层，去除带，在该层中形成到达电极的开口，在该层上形成导电电路，并形成 打开连接到电极的层a通孔。

公开(公告)号：US20110157763A1

公开(公告)日：2011-06-30

申请号：US13042686

申请日：2011-03-08

Applicant: Hiroshi YAMAMOTO ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

Inventor： Hiroshi YAMAMOTO ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC: H01G4/224 ,  H01G4/30

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract translation: 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。

公开(公告)号：US20110090615A1

公开(公告)日：2011-04-21

申请号：US12951739

申请日：2010-11-22

Applicant: Motohiko SATO ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Karahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

Inventor： Motohiko SATO ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Karahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

IPC: H01G4/30

CPC classification number: H05K1/0231 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

公开(公告)号：US07863662B2

公开(公告)日：2011-01-04

申请号：US11643871

申请日：2006-12-22

Applicant: Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

Inventor： Motohiko Sato ,  Kazuhiro Hayashi ,  Kenji Murakami ,  Motonobu Kurahashi ,  Yusuke Kaieda ,  Jun Otsuka ,  Manabu Sato

IPC: H01L21/02

CPC classification number: H05K1/0231 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract translation: 一种电容器，其具有电容器，所述电容器包括：电容器主体，包括多个电介质层和设置在所述不同电介质层之间的内部电极层，其中所述电容器本体在所述电容器主体的至少一个侧面中， 从所述电容器主体的第一主面和位于与所述第一主面相反的一侧的第二主面中的至少一个在所述电容器本体的厚度方向上延伸的凹部。

公开(公告)号：US07696442B2

公开(公告)日：2010-04-13

申请号：US11445288

申请日：2006-06-02

Applicant: Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

Inventor： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

IPC: H05K1/16

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wiring board comprising: a core board including a core body and a ceramic sub-core which is accommodated in a sub-core accommodation space that is a through-hole that communicates with major surfaces of the core body or a recess having an opening in a first major surface of the core body; and wiring laminates each formed by resin insulating layers and conductor layers laminated on each of major surfaces of the core board, wherein: a groove-filling portion which fills a gap between the core body and the ceramic sub-core is integral with a lowest resin insulating layer of the first-major-surface-side wiring laminate; and via conductors that are connected to respective conductor patterns formed on a first major surface of the ceramic sub-core penetrate through the lowest resin insulating layer.

Abstract translation: 一种布线板，包括：芯板，其包括芯体和陶瓷子芯，所述芯体容纳在与所述芯体的主表面连通的通孔的子芯容纳空间中，或者具有开口的凹部 核心体的第一个主要表面; 以及由层叠在芯板的各主表面上的树脂绝缘层和导体层形成的布线层叠体，其中，填充芯体与陶瓷副芯之间的间隙的沟槽填充部与最低树脂 第一主表面侧布线层叠体的绝缘层; 并且连接到形成在陶瓷子芯的第一主表面上的相应导体图案的通孔导体穿透最低树脂绝缘层。

公开(公告)号：US20090268373A1

公开(公告)日：2009-10-29

申请号：US12497198

申请日：2009-07-02

Applicant: Motohiko SATO ,  Kazuhiro HAYASHI ,  Akifumi TOSA ,  Kenji MURAKAMI ,  Tomohide YAMADA ,  Motonobu KURAHASHI

Inventor： Motohiko SATO ,  Kazuhiro HAYASHI ,  Akifumi TOSA ,  Kenji MURAKAMI ,  Tomohide YAMADA ,  Motonobu KURAHASHI

IPC: H01G4/228 ,  H01G7/00

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/435

Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.

Abstract translation: 一种电容器，包括：多个叠层电介质层; 多个内部电极层，各自设置在相互相邻的电介质层之间; 以及分别设置在电介质层之间的虚设电极层，其设置在比内部电极层更靠近电介质层的外周侧的一侧并且与内部电极层分离。