Abstract:
A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.
Abstract:
Computer cabinets, such as supercomputer cabinets, having progressive air velocity cooling systems are described herein. In one embodiment, a computer cabinet includes an air mover positioned beneath a plurality of computer module compartments. The computer module compartments can be arranged in tiers with the computer modules in each successive tier being positioned closer together than the computer modules in the tier directly below. The computer cabinet can also include one or more shrouds, flow restrictors, and/or sidewalls that further control the direction and/or speed of the cooling air flow through the cabinet.
Abstract:
A system and method for cooling a plurality of electronics cabinets having horizontally positioned electronics assemblies. The system includes at least one blower configured to direct air horizontally across the electronics assemblies, and at least one intercooler configured to extract heat from the air flow such that the system is room neutral, meaning that the ambient temperature remains constant during operation of the system. A plurality of chassis backplanes and power supplies may also include an intercooler, wherein the intercoolers are electronically controlled such that the system is room neutral.
Abstract:
An improved method for the prevention of deadlock in a massively parallel processor (MPP) system wherein, prior to a process sending messages to another process running on a remote processor, the process allocates space in a deadlock-avoidance FIFO. The allocated space provides a “landing zone” for requests that the software process (the application software) will subsequently issue using a remote-memory-access function. In some embodiments, the deadlock-avoidance (DLA) function provides two different deadlock-avoidance schemes: controlled discard and persistent reservation. In some embodiments, the software process determines which scheme will be used at the time the space is allocated.
Abstract:
A method and system in a computer system for dynamically providing a graphical representation of a data store of entries via a matrix interface is disclosed. A dynamic graph system provides a matrix interface that exposes to an application program a graphical representation of data stored in a data store such as a semantic database storing triples. To the application program, the matrix interface represents the graph as a sparse adjacency matrix that is stored in compressed form. Each entry of the data store is considered to represent a link between nodes of the graph. Each entry has a first field and a second field identifying the nodes connected by the link and a third field with a value for the link that connects the identified nodes. The first, second, and third fields represent the rows, column, and elements of the adjacency matrix.
Abstract:
A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.
Abstract:
Computer systems having heat exchangers for cooling computer components are disclosed herein. The computer systems include a computer cabinet having an air inlet, an air outlet spaced apart from the air inlet, and a plurality of computer module compartments positioned between the air inlet and the air outlet. The air inlet, the air outlet, and the computer module compartments define an air flow path through the computer cabinet. The computer systems also include a heat exchanger positioned between two adjacent computer module compartments. The heat exchanger includes a plurality of heat exchange elements canted relative to the air flow path.
Abstract:
A method and system in a computer system for dynamically providing a graphical representation of a data store of entries via a matrix interface is disclosed. A dynamic graph system provides a matrix interface that exposes to an application program a graphical representation of data stored in a data store such as a semantic database storing triples. To the application program, the matrix interface represents the graph as a sparse adjacency matrix that is stored in compressed form. Each entry of the data store is considered to represent a link between nodes of the graph. Each entry has a first field and a second field identifying the nodes connected by the link and a third field with a value for the link that connects the identified nodes. The first, second, and third fields represent the rows, column, and elements of the adjacency matrix.
Abstract:
A system for updating an index into a tuple table of tuples is provided. An indexing system updates an index into a tuple table using fine-grain locking of the index. The index includes a values table with an entry for each index value of an index field that references a value-tuple table that includes, for each tuple with the index value, a row that identifies a tuple of the tuple table with that indexed value. After a new tuple is added to the tuple table with a value, the index is updated by locking the entry in the values table, updating the value-tuple table for the value, and then unlocking the entry. When the index is accessed for locating tuples with a value, the accessor locks the entry in the values table for the value, uses the value-tuple table to locate the tuples, and unlocks the entry.
Abstract:
Systems and methods for synchronizing a system clock signal with a reference clock signal having a reduced phased offset to improve operating speeds of integrated circuits. This is accomplished by generating delayed system and reference clock signals by using the system and reference clock signals. The generated delayed clock signals are then monitored to determine the arrival of the raising and falling edges of the delayed clock signals. The system clock signal is then compensated based on the determination of the arrival of the delayed clock signals to substantially synchronize the system clock signal with respect to the reference clock signal.