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公开(公告)号：US11367751B2
公开(公告)日：2022-06-21
申请号：US16948575
申请日：2020-09-23
Applicant: Unity Semiconductor Corporation
Inventor： Bruce Lynn Bateman
Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
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公开(公告)号：US11287246B2
公开(公告)日：2022-03-29
申请号：US16967649
申请日：2019-01-25
Inventor： Jean-François Boulanger , Stéphane Godny
Abstract: A method and related device for measuring the profile of a surface of an object to be measured having zones made from at least two different materials, the object to be measured forming part of a plurality of substantially identical objects, the plurality of objects also including at least one reference object having at least one reference surface, the method including the following steps: determining a correction function, from a first profile signal of a first reference surface and a second profile signal from a second reference surface, the second reference surface being metallized; acquiring a profile signal from the surface of the object to be measured; and applying the correction function to the profile signal from the surface of the object to be measured to obtain a corrected profile signal; the profile signals being obtained from interferometric measurements.
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公开(公告)号：US11144218B2
公开(公告)日：2021-10-12
申请号：US17031640
申请日：2020-09-24
Applicant: Unity Semiconductor Corporation
Inventor： Chang Hua Siau
Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
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74.发明授权公开(公告)号：US11092644B2
公开(公告)日：2021-08-17
申请号：US16087056
申请日：2017-03-14
Applicant: UNITY SEMICONDUCTOR
Inventor： Philippe Gastaldo , Mayeul Durand De Gevigney , Tristan Combier
IPC: G01R31/308 , G01R31/28
Abstract: A method for inspecting a wafer including: rotating the wafer about an axis of symmetry (X) perpendicular to a main wafer surface (S); emitting, from a light source coupled with an interferometric device, two incident light beams, to form, at the intersection between the two beams, a measurement volume (V) containing interference fringes so that a region of the main surface (S) of the wafer passes through a fringe, the dimension (Dy) of the measurement volume in a radial direction of the wafer being between 5 and 100 μm; collecting a portion of the light scattered by the wafer region; acquiring the collected light and emitting a signal representing the variation in the collected light intensity as a function of time; and detecting, a frequency component in the collected light, the frequency being the time signature of a defect passage through the measurement volume.
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公开(公告)号：US20210239462A1
公开(公告)日：2021-08-05
申请号：US16967649
申请日：2019-01-25
Inventor： Jean-François BOULANGER , Stéphane GODNY
Abstract: A method and related device for measuring the profile of a surface of an object to be measured having zones made from at least two different materials, the object to be measured forming part of a plurality of substantially identical objects, the plurality of objects also including at least one reference object having at least one reference surface, the method including the following steps: determining a correction function, from a first profile signal of a first reference surface and a second profile signal from a second reference surface, the second reference surface being metallized; acquiring a profile signal from the surface of the object to be measured; and applying the correction function to the profile signal from the surface of the object to be measured to obtain a corrected profile signal; the profile signals being obtained from interferometric measurements.
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Patent Agency Ranking
公开(公告)号：US10803935B2
公开(公告)日：2020-10-13
申请号：US16429411
申请日：2019-06-03
Applicant: Unity Semiconductor Corporation
Inventor： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
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公开(公告)号：US10354726B2
公开(公告)日：2019-07-16
申请号：US16126101
申请日：2018-09-10
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号：US10050086B2
公开(公告)日：2018-08-14
申请号：US15231331
申请日：2016-08-08
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Lidia Vereen , Bruce L. Bateman , David A. Eggleston , Louis C. Parrillo
IPC: H01L45/00 , H01L27/24 , H01L23/528
Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
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79.发明申请公开(公告)号：US20180197604A1
公开(公告)日：2018-07-12
申请号：US15868234
申请日：2018-01-11
Applicant: Unity Semiconductor Corporation
Inventor： Chang Hua Siau , Bruce Lynn Bateman
CPC classification number: G11C13/0069 , G11C5/06 , G11C5/08 , G11C7/00 , G11C7/04 , G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0097 , G11C16/24 , G11C2213/71
Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.
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80.发明申请公开(公告)号：US20180182454A1
公开(公告)日：2018-06-28
申请号：US15823270
申请日：2017-11-27
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Robert Norman
IPC: G11C13/00
Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
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