公开(公告)号：US20190051701A1

公开(公告)日：2019-02-14

申请号：US16042359

申请日：2018-07-23

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce L. Bateman ,  David A. Eggleston ,  Louis C. Parrillo

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US20200258940A1

公开(公告)日：2020-08-13

申请号：US16735394

申请日：2020-01-06

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce Lynn Bateman ,  David Alan Eggleston ,  Louis C. Parrillo

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US09029827B2

公开(公告)日：2015-05-12

申请号：US14062609

申请日：2013-10-24

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce Lynn Bateman ,  Louis Parrillo ,  Elizabeth Friend ,  David Eggleston

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/145 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract translation: 在一个示例中，通过例如提供电介质层，在电介质层中形成空隙，以及形成第一两端电阻存储单元的一部分和第二两端的一部分，形成单个镶嵌结构 电阻记忆体在空隙内。 两端电阻式存储单元的部分可以垂直地堆叠在空隙内。

公开(公告)号：US10050086B2

公开(公告)日：2018-08-14

申请号：US15231331

申请日：2016-08-08

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Lidia Vereen ,  Bruce L. Bateman ,  David A. Eggleston ,  Louis C. Parrillo

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US20170033158A1

公开(公告)日：2017-02-02

申请号：US15231331

申请日：2016-08-08

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Lidia Vereen ,  Bruce L. Bateman ,  David A. Eggleston ,  Louis C. Parrillo

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract translation: 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的水平线对之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。

公开(公告)号：US20140231741A1

公开(公告)日：2014-08-21

申请号：US14062609

申请日：2013-10-24

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce Lynn Bateman ,  Louis Parillo ,  Elizabeth Friend ,  David Eggleston

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract translation: 在一个示例中，通过例如提供电介质层，在电介质层中形成空隙，以及形成第一两端电阻存储单元的一部分和第二两端的一部分，形成单个镶嵌结构 电阻记忆体在空隙内。 两端电阻式存储单元的部分可以垂直地堆叠在空隙内。

公开(公告)号：US10529778B2

公开(公告)日：2020-01-07

申请号：US16042359

申请日：2018-07-23

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce L. Bateman ,  David A. Eggleston ,  Louis C. Parrillo

IPC: H01L21/20 ,  H01L27/24 ,  H01L45/00 ,  H01L23/528

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.