公开(公告)号：US09054190B2

公开(公告)日：2015-06-09

申请号：US14263708

申请日：2014-04-28

Applicant: Intel Corporation

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

公开(公告)号：US20150072498A1

公开(公告)日：2015-03-12

申请号：US14543841

申请日：2014-11-17

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Robert S. Chau ,  Marko Radosavljevic ,  Han Wui Then ,  Scott B. Clendenning ,  Ravi Pillarisetty

IPC: H01L29/66 ,  H01L21/223 ,  H01L21/228 ,  H01L21/28

CPC classification number: H01L29/66803 ,  B82Y10/00 ,  H01L21/2233 ,  H01L21/228 ,  H01L21/28264 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

Abstract: A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

Abstract translation: 具有非平面晶体管沟道区域的III-V族半导体表面的高k栅极电介质界面是非定向掺杂氮气的。 在纳米线实施例中，通过将栅极电介质暴露于液体，蒸气，气体，等离子体或固态氮源，在共形栅极电极沉积之前或同时进行高k栅介质界面的非定向氮掺杂 。 在实施例中，栅极电极金属被共形沉积在栅极电介质上，并且执行退火以沿着非平面III-V半导体界面均匀地在栅极电介质内积累氮。

公开(公告)号：US12302618B2

公开(公告)日：2025-05-13

申请号：US17458097

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Samuel James Bader ,  Pratik Koirala ,  Nicole K. Thomas ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L29/267 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H10D30/01 ,  H10D30/47 ,  H10D62/82 ,  H10D64/00

Abstract: An integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width and a first height. A second trench is in the substrate, the second trench having a second width and a second height. The second width is greater than the first width, and the second height is greater than the first height. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate.

公开(公告)号：US20250113561A1

公开(公告)日：2025-04-03

申请号：US18476624

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Marko Radosavljevic ,  Hsu-Yu Chang ,  Scott M. Mokler ,  Stephanie Chin ,  Walid M. Hafez

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786

Abstract: In stacked transistor device, such as a complementary field-effect-transistor (CFET) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the PMOS layer, and a compressive material is deposited in second isolation region in the NMOS layer. The strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. In some cases, in one or both of the isolation regions, a liner material is included between the strain material and the source and drain regions. Certain embodiments provide independent tuning of strain forces in a stacked transistor device. Different materials are selected for different layers in the stacked device to provide favorable performance enhancement or tuning (e.g., adjustment of the threshold voltage) in NMOS and PMOS layers.

公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US20250006791A1

公开(公告)日：2025-01-02

申请号：US18346227

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dominique A. Adams ,  Gauri Auluck ,  Pratyush P. Buragohain ,  Scott B. Clendenning ,  Punyashloka Debashis ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

公开(公告)号：US20240194672A1

公开(公告)日：2024-06-13

申请号：US18064362

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Bharath Bangalore Rajeeva ,  Manish Chandhok ,  Gurpreet Singh ,  Kevin Huggins ,  Eungnak Han ,  Florian Gstrein ,  Marko Radosavljevic

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L23/522 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0271 ,  H01L23/5226 ,  H01L29/1033 ,  H01L29/42364

Abstract: An IC device may include a first conductive structure in a first section and a second conductive structure in a second section. The second conductive structure is in parallel with the first conductive structure in a first direction. A dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction. The first conductive structure may be coupled to a channel region of a transistor. The second conductive structure may be coupled to a channel region of another transistor. A first structure comprising a first dielectric material may be over the first conductive structure. A second structure comprising a second dielectric material may be over the second section. A third structure comprising the first dielectric material may be over the second conductive structure and be at least partially surrounded by the second structure.

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US11881511B2

公开(公告)日：2024-01-23

申请号：US16226162

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Johann C. Rode ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785

Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.