公开(公告)号：US20120097442A1

公开(公告)日：2012-04-26

申请号：US13269212

申请日：2011-10-07

Applicant: Hideaki YOSHIMURA ,  Kenji Iida ,  Yasutomo Maehara

Inventor： Hideaki YOSHIMURA ,  Kenji Iida ,  Yasutomo Maehara

IPC: H05K1/11 ,  B27N3/06

CPC classification number: H05K1/0366 ,  B29C70/46 ,  B29C70/545 ,  B29L2031/3425 ,  H01L23/145 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/0097 ,  H05K2201/029 ,  H01L2924/00

Abstract: A printed circuit board includes a cell portion which includes cells having a plurality of through bores are arranged in a base material; and a base material portion which exists around an outer edge of the cell portion. The base material is formed of a prepreg, the prepreg includes a fiber material in which fiber threads are oriented in a first direction and in a second direction which is perpendicular to the first direction, and a resin material in which the fiber material is impregnated. The through bores are arranged along a third direction between the first direction and the second direction, wherein one side of the outer edges of the cell extends along the third direction.

Abstract translation: 印刷电路板包括：细胞部分，其包括具有多个通孔的细胞，其布置在基材中; 以及围绕电池部分的外边缘存在的基材部分。 基材由预浸料坯形成，预浸料坯包括纤维材料，其中纤维线沿第一方向和与第一方向垂直的第二方向定向，以及其中浸渍纤维材料的树脂材料。 通孔沿着第一方向和第二方向之间的第三方向布置，其中电池的外边缘的一侧沿着第三方向延伸。

公开(公告)号：US20120064236A1

公开(公告)日：2012-03-15

申请号：US13321930

申请日：2010-05-24

Applicant: Yoshinori Matsuzaki ,  Kazuhiko Fujita ,  Masaya Tashiro ,  Shinya Kobayashi

Inventor： Yoshinori Matsuzaki ,  Kazuhiko Fujita ,  Masaya Tashiro ,  Shinya Kobayashi

IPC: B05D3/12 ,  B05C11/02 ,  B05C11/00

CPC classification number: H05K1/0366 ,  H05K2201/029 ,  H05K2203/0759 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: The present invention has been aimed to propose a process and a device of fabricating a prepreg for a printed circuit board which are capable of controlling respective thicknesses of resin layers on the opposite surfaces of a resultant prepreg, removing air bubbles from the resultant prepreg, and improving productivity.The present invention is a process of resin-coating the opposite surfaces of an elongated substrate sheet 3. The process includes the steps of: feeding the substrate sheet 3 while tensioning the same in a feeding direction along the length of the substrate sheet 3; coating, by the coating head 2 of the first dispenser 1a, one surface of the substrate sheet 3 with the fluid resin 4 while pressing against the one surface to bend the substrate sheet 3; and subsequently coating, by the coating head 2 of the second dispenser 1b, the other surface of the substrate sheet 3 with the fluid resin 4 while pressing against the other surface to bend the substrate sheet 3. A die coater and a roll coater can be used as the first dispenser 1a and the second dispenser 1b.

Abstract translation: 本发明的目的在于提出一种制造用于印刷电路板的预浸料坯的方法和装置，其能够控制所得预浸料坯的相对表面上的树脂层的各自厚度，从所得预浸料中除去气泡，以及 提高生产率。 本发明是一种对细长基片3的相对表面进行树脂涂覆的方法。该方法包括以下步骤：沿着基片3的长度沿着馈送方向张紧基片3; 通过第一分配器1a的涂覆头2将基片3的一个表面与流体树脂4同时压在一个表面上以弯曲基片3; 并且随后通过第二分配器1b的涂覆头2将基材片3的另一个表面用流体树脂4挤压，同时压靠另一个表面以弯曲基材片3.模具涂布机和辊涂机可以是 用作第一分配器1a和第二分配器1b。

公开(公告)号：US08035034B2

公开(公告)日：2011-10-11

申请号：US12118658

申请日：2008-05-09

Applicant: Yu-Hsu Lin ,  Jeng-Da Wu ,  Chih-Hang Chao

Inventor： Yu-Hsu Lin ,  Jeng-Da Wu ,  Chih-Hang Chao

IPC: H05K1/03

CPC classification number: H05K1/0366 ,  H05K1/0245 ,  H05K1/0248 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09281

Abstract: A printed circuit board includes a base and a signal trace laid on the base. The signal trace includes a plurality of straight line segments parallel to the first fibers. The signal trace is laid on the base in such a manner that the line segments of the signal trace mapped on the base partly superpose the first fibers and partly superpose gaps between two adjacent first fibers.

Abstract translation: 印刷电路板包括放置在基座上的基座和信号迹线。 信号迹线包括平行于第一光纤的多条直线段。 信号迹线以这样的方式铺设在基座上，使得映射在基座上的信号迹线的线段部分地叠加第一光纤并且部分地叠加两个相邻的第一光纤之间的间隙。

公开(公告)号：US20110232953A1

公开(公告)日：2011-09-29

申请号：US13074144

申请日：2011-03-29

Applicant: Takeshi Oga ,  Katsura Hayashi

Inventor： Takeshi Oga ,  Katsura Hayashi

IPC: H05K1/02

CPC classification number: H05K3/4602 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/427 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/029 ,  H05K2201/0769 ,  H05K2201/09481 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/10674 ,  H05K2201/2072

Abstract: According to one embodiment of the invention, a circuit board comprises an insulating layer including a resin material, a plurality of inorganic insulating particles, and a penetrating hole. The circuit board further comprises a penetrating conductor disposed in the penetrating hole. The insulating layer includes a resin insulating portion having the plurality of inorganic insulating particles dispersed in the resin material. The insulating layer further includes an inorganic insulating portion interposed between the resin insulating portion and the penetrating conductor and made of the same material as the plurality of inorganic insulating particles.

Abstract translation: 根据本发明的一个实施例，电路板包括包括树脂材料，多个无机绝缘颗粒和穿透孔的绝缘层。 电路板还包括布置在穿透孔中的穿透导体。 绝缘层包括具有分散在树脂材料中的多个无机绝缘粒子的树脂绝缘部分。 绝缘层还包括介于树脂绝缘部分和穿透导体之间并由与多个无机绝缘颗粒相同的材料制成的无机绝缘部分。

公开(公告)号：US08022310B2

公开(公告)日：2011-09-20

申请号：US12193311

申请日：2008-08-18

Applicant: Toru Okazaki ,  Hideo Suzuki

Inventor： Toru Okazaki ,  Hideo Suzuki

IPC: H05K1/03

CPC classification number: H05K3/4688 ,  H05K1/0271 ,  H05K1/0366 ,  H05K2201/029 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: The present invention provides a multilayer wiring board in which warpage during reflow soldering can be reduced even if there is no sufficient space for disposing a dummy pattern or if a dummy pattern cannot be disposed. A difference between the ratios of copper remaining in wiring layers causes a difference between the amounts of thermal expansion of the wiring layers. The fiber bundle content of at least one resin base material layer is made different from that of the other resin base material layers, to cause a difference between the amounts of thermal expansion of the resin base material layers. This difference between the amounts of thermal expansion of the resin base material layers is used to cancel the difference between the amounts of thermal expansion of the wiring layers. Thus, warpage of the board during reflow soldering is reduced.

Abstract translation: 本发明提供一种多层布线基板，其中即使没有足够的空间来设置虚设图案，或者如果不能设置虚设图案，则可以降低回流焊接期间的翘曲。 布线层中残留的铜的比例之间的差异导致布线层的热膨胀量之间的差异。 使至少一个树脂基材层的纤维束含量与其它树脂基材层的纤维束含量不同，导致树脂基材层的热膨胀量之间的差异。 使用树脂基材层的热膨胀量之间的这种差异来消除布线层的热膨胀量之差。 因此，在回流焊接期间板的翘曲减小。

公开(公告)号：US08018066B2

公开(公告)日：2011-09-13

申请号：US12753521

申请日：2010-04-02

Applicant: Eiji Hayashi ,  Kyo Go ,  Kozo Harada ,  Shinji Baba

Inventor： Eiji Hayashi ,  Kyo Go ,  Kozo Harada ,  Shinji Baba

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/373 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L24/81 ,  H01L2021/6015 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81909 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/0366 ,  H05K3/4602 ,  H05K2201/029 ,  H01L2924/0132 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/00014

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained.As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract translation: 即使省略了加强件，也可以获得能够防止布线基板发生扭曲和变形的半导体装置。 对于具有布线基板的半导体器件，通过其与布线基板进行倒装芯片接合的半导体芯片和粘附到半导体芯片的背面的散热器，并且省略了用于加强布线的加强件 基板并且保持散热器的表面平滑度，布线基板具有分别形成直径不同的通孔的多个绝缘基板，并且每个绝缘基板包含玻璃布。

公开(公告)号：US07967938B2

公开(公告)日：2011-06-28

申请号：US12779415

申请日：2010-05-13

Applicant: James D Smith ,  Gary Stevens ,  John W Wood

Inventor： James D Smith ,  Gary Stevens ,  John W Wood

IPC: D06M23/08

CPC classification number: H01B3/04 ,  C03C25/1095 ,  H01B3/084 ,  H05K1/0366 ,  H05K2201/0175 ,  H05K2201/029 ,  Y10T156/10 ,  Y10T442/2033 ,  Y10T442/2418 ,  Y10T442/2426 ,  Y10T442/2475 ,  Y10T442/2861 ,  Y10T442/2893 ,  Y10T442/291 ,  Y10T442/2918 ,  Y10T442/2992 ,  Y10T442/3382 ,  Y10T442/3935 ,  Y10T442/3976

Abstract: The present invention facilitates the thermal conductivity of fabrics by surface coating of the fabrics with high thermal conductivity materials 6. The fabrics may be surface coated when they are individual fibers or strands 4, bundles of strands, formed fabric or combinations therefore. A particular type of fibrous matrix used with the present invention is glass. Some fabrics may be a combination of more than one type of material, or may have different materials in alternating layers. HTC coatings of the present invention include diamond like coatings (DLC) and metal oxides, nitrides, carbides and mixed stoichiometric and non-stoichiometric combinations that can be applied to the host matrix.

Abstract translation: 本发明通过具有高导热性材料6的织物的表面涂覆来促进织物的导热性。当织物是单独的纤维或股线4时，织物可以被表面涂覆，因此，股线束，成形织物或组合。 与本发明一起使用的特定类型的纤维基质是玻璃。 一些织物可以是多于一种类型的材料的组合，或者可以在交替层中具有不同的材料。 本发明的HTC涂层包括金刚石涂层（DLC）和金属氧化物，氮化物，碳化物以及可以施加到主体基质上的混合化学计量和非化学计量组合。

公开(公告)号：US20110078895A1

公开(公告)日：2011-04-07

申请号：US12897006

申请日：2010-10-04

Applicant: Makoto SUWADA

Inventor： Makoto SUWADA

IPC: H05K3/00

CPC classification number: H05K3/0008 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0269 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/0005 ,  H05K3/0082 ,  H05K3/064 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09272 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: A method of manufacturing a wiring substrate includes forming a conducting layer on a first insulating layer including a first glass cloth; forming a photosensitive resist layer on the conducting layer; recognizing a first origin position on the first insulating layer; forming a mask on the resist layer by positioning the mask with respect to the first origin position, the mask being formed so as to position wiring patterns only on positions overlapping the first glass cloth in a planar view; and exposing the resist layer via the mask and forming the wiring patterns only on the positions overlapping the first glass cloth in the planar view.

Abstract translation: 制造布线基板的方法包括在包括第一玻璃布的第一绝缘层上形成导电层; 在导电层上形成光敏抗蚀剂层; 识别第一绝缘层上的第一原点位置; 通过将掩模相对于第一原始位置定位而在抗蚀剂层上形成掩模，掩模形成为仅在平面图中与布置图案重叠的位置上布置布线图案; 并且经由掩模曝光抗蚀剂层，并且仅在平面图中与第一玻璃布重叠的位置上形成布线图案。

公开(公告)号：US20110045730A1

公开(公告)日：2011-02-24

申请号：US12938238

申请日：2010-11-02

Applicant: Swatee N. Surve

Inventor： Swatee N. Surve

IPC: D04B1/24 ,  D04B21/00 ,  D04B21/14

CPC classification number: H01Q1/273 ,  A41D1/002 ,  A61B5/6804 ,  A61B2562/0219 ,  C23C4/04 ,  C23C24/08 ,  D02G3/00 ,  D03D1/0088 ,  D03D15/00 ,  D03D15/005 ,  D06M10/005 ,  D06M10/06 ,  D10B2201/02 ,  D10B2201/24 ,  D10B2211/02 ,  D10B2211/04 ,  D10B2321/022 ,  D10B2331/02 ,  D10B2331/04 ,  D10B2401/18 ,  D10B2501/00 ,  D10B2501/042 ,  D10B2501/043 ,  H01L27/12 ,  H01L29/0657 ,  H01L29/7317 ,  H05K1/00 ,  H05K1/038 ,  H05K1/16 ,  H05K2201/029 ,  Y10S2/905 ,  Y10T428/249921 ,  Y10T428/249953 ,  Y10T442/30 ,  Y10T442/40

Abstract: Fibers, such as textile fibers, having electrical components deposited thereon. More particularly, one or more electrical components are formed directly onto the surface of at least one fiber. The fiber having the electrical component formed thereon may then be interlaced with other fibers to form a larger piece of fabric, which can be employed to produce an article of clothing. A group of transistors and piezoelectric components forming an accelerometer may be woven onto one or more natural or synthetic fibers. The fibers may then be employed as the warp, weft, or both, of a woven piece of fabric, or used to form a knitted piece of fabric. The fabric piece can then be cut and sewn to form a wearable item, such as a shirt, a pair of pants, a hat, or the upper piece of a shoe that includes the accelerometer.

Abstract translation: 纤维，如纺织纤维，其上沉积有电子部件。 更具体地，一个或多个电气部件直接形成在至少一根纤维的表面上。 然后可以将其中形成有电气部件的纤维与其它纤维交错，以形成较大的织物片，其可用于生产衣物。 形成加速度计的一组晶体管和压电元件可以编织在一个或多个天然或合成纤维上。 然后纤维可以用作织造织物的经纱，纬纱或两者，或用于形成编织的织物片。 然后可以将织物片切割并缝制以形成可穿戴物品，例如衬衫，一条裤子，帽子或包括加速度计的鞋子的上部件。

公开(公告)号：US20110036448A1

公开(公告)日：2011-02-17

申请号：US12989461

申请日：2009-04-22

Applicant: Liesbeth Van Pieterson ,  Rabin Bhattacharya ,  Koen Van Os

Inventor： Liesbeth Van Pieterson ,  Rabin Bhattacharya ,  Koen Van Os

IPC: D03D15/00

CPC classification number: H05K1/0269 ,  H05K1/0266 ,  H05K1/038 ,  H05K1/189 ,  H05K3/303 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/083 ,  H05K2201/09918 ,  H05K2201/10106 ,  H05K2203/166 ,  Y02P70/613

Abstract: The invention relates to a textile (1) for mounting a first electronic component at a first designated position (121) on the textile, and for mounting a second electronic component at a second designated position (122) on the textile, the textile comprising a first marker pattern (111, 112) associated with the first designated position, and a second marker pattern (113, 114) associated with the second designated position. With the textile according to the invention, an electronic textile can be reliably manufactured using conventional equipment known from the electronics assembly industry, such as a pick-and-place apparatus, whereby the electronic components are properly provided at their respective designated positions on the textile.

Abstract translation: 本发明涉及一种用于将第一电子部件安装在织物上的第一指定位置（121）并用于将第二电子部件安装在纺织品上的第二指定位置（122）的纺织品（1），所述纺织品包括 与第一指定位置相关联的第一标记图案（111,112）以及与第二指定位置相关联的第二标记图案（113,114）。 对于根据本发明的纺织品，可以使用从电子组装工业已知的常规设备（例如拾放设备）可靠地制造电子织物，由此电子部件在其各自的指定位置适当地设置在纺织品上 。