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    PRINTED CIRCUIT BOARD STRUCTURE
    71.
    发明申请
    PRINTED CIRCUIT BOARD STRUCTURE 审中-公开
    印刷电路板结构

    公开(公告)号：US20160135291A1

    公开(公告)日：2016-05-12

    申请号：US14932944

    申请日：2015-11-04

    Applicant: Hsin-Ting Liu ,  Ming-Jen Lin ,  Chun-Hung Chen

    Inventor： Hsin-Ting Liu ,  Ming-Jen Lin ,  Chun-Hung Chen

    IPC: H05K1/02 ,  H05K1/11

    CPC classification number: H05K1/117 ,  H05K1/0253 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/094

    Abstract: A printed circuit board structure includes a main body and a connecting interface. The connecting interface connects and is located at a side of the main body. The connecting interface includes conductive layers and insulation layers. The conductive layers at least include a first, a second, a third, a fourth conductive layer. The insulation layers at least include a first, a second, a third insulation layers. The insulation layers and the conductive layers are alternately disposed. The first insulation layer is located between the first conductive layer and the second conductive layer. The first conductive layer and the second conductive layer are partially overlapped in their orthographic projections on the first insulation layer. The second insulation layer is located between the second conductive layer and the third conductive layer. The third insulation layer is located between the third conductive layer and the fourth conductive layer.

    Abstract translation: 印刷电路板结构包括主体和连接界面。 连接接口连接并位于主体的一侧。 连接界面包括导电层和绝缘层。 导电层至少包括第一，第二，第三，第四导电层。 绝缘层至少包括第一绝缘层，第二绝缘层，第二绝缘层。 绝缘层和导电层交替设置。 第一绝缘层位于第一导电层和第二导电层之间。 第一导电层和第二导电层在其第一绝缘层上的正投影部分重叠。 第二绝缘层位于第二导电层和第三导电层之间。 第三绝缘层位于第三导电层和第四导电层之间。

    CAPACITOR-INCORPORATED SUBSTRATE AND COMPONENT-INCORPORATED WIRING SUBSTRATE
    73.
    发明申请
    CAPACITOR-INCORPORATED SUBSTRATE AND COMPONENT-INCORPORATED WIRING SUBSTRATE 有权
    电容器合并基板和元器件并联导线基板

    公开(公告)号：US20120241906A1

    公开(公告)日：2012-09-27

    申请号：US13389364

    申请日：2010-08-04

    Applicant: Naoya Nakanishi

    Inventor： Naoya Nakanishi

    IPC: H01L29/92

    CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10674

    Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50. The capacitor-incorporated wiring substrate has a first via-conductor group to be connected to a first electric potential, and a second via-conductor group to be connected to a second electric potential. A first electrode pattern connected to the first via-conductor group, and a plurality of second electrode patterns connected to the second via-conductor group, are formed in a front-surface electrode layer 51 of the capacitor 50. A first conductor pattern connected to the first via-conductor group, and a plurality of second conductor patterns connected to the second via-conductor group, are formed in a proximate conductor layer 31 of a first buildup layer 12. Each of the second electrode patterns and each of the second conductor patterns connect a predetermined number of via electrodes and extend in such a manner as to be orthogonal to each other.

    Abstract translation: 本发明的目的是提供一种通过确保即使在通孔导体组中发生故障连接而产生电位的路径也可以提高连接可靠性的电容器配线布线基板。 在本发明的电容器配线基板中，电容器50容纳在芯体11中，在电容器50的上侧和下侧分别形成有第一和第二堆积层12和13。 电容器配合的布线基板具有要连接到第一电位的第一通孔导体组和要连接到第二电位的第二通孔导体组。 连接到第一通孔导体组的第一电极图案和连接到第二通孔导体组的多个第二电极图案形成在电容器50的前表面电极层51中。第一导体图案连接到 第一通孔导体组以及连接到第二通孔导体组的多个第二导体图案形成在第一堆积层12的邻近的导体层31中。每个第二电极图案和每个第二导体 图案连接预定数量的通孔电极并以彼此正交的方式延伸。

    Continuously Referencing Signals over Multiple Layers in Laminate Packages
    77.
    发明申请
    Continuously Referencing Signals over Multiple Layers in Laminate Packages 审中-公开
    连续引用层叠软件包中多层信号

    公开(公告)号：US20080093726A1

    公开(公告)日：2008-04-24

    申请号：US11551888

    申请日：2006-10-23

    Applicant: Francesco Preda ,  Lloyd A. Walls

    Inventor： Francesco Preda ,  Lloyd A. Walls

    IPC: H01L23/12

    CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

    Abstract translation: 用于在层压封装中连续地参考多层信号的机构提供了用于从一层到另一层的信号的连续路径，同时使用用于封装的所有区域的理想电压基准并且仍避免电压基准中的不连续性。 参考平面调整引擎分析封装设计，并为封装的所有区域（包括特定芯片裸片下的区域）和不在芯片裸片下的区域识别理想的顶层平面。 参考平面调整引擎然后修改封装设计以重新定位层之间的接地层，源电压平面，信号面和通孔，以保持连续的电压基准，而不管顶层如何。 参考平面调整引擎将所形成的混合电压平面封装设计提供给设计分析引擎。 包装制造系统制造包装。

    CIRCUIT BOARDS AND ASSEMBLY METHODS
    78.
    发明申请
    CIRCUIT BOARDS AND ASSEMBLY METHODS 审中-公开
    电路板和组装方法

    公开(公告)号：US20060268531A1

    公开(公告)日：2006-11-30

    申请号：US11427733

    申请日：2006-06-29

    Applicant: Steve Van Kirk

    Inventor： Steve Van Kirk

    IPC: H01R12/16

    CPC classification number: H05K1/162 ,  H05K2201/09236 ,  H05K2201/09345

    Abstract: A method of forming a circuit board having first and second conductive layers with a dielectric layer, or of forming a capacitor having a dielectric layer in a circuit board with first and second conducting layers, may include forming a first interstice in the first conductive layer, forming a second interstice engaging the first interstice in the second conductive layer, and inserting the dielectric layer between the first and second interstices.

    Abstract translation: 一种形成具有介电层的第一和第二导电层或者在具有第一和第二导电层的电路板中形成具有电介质层的电容器的电路板的方法可以包括在第一导电层中形成第一间隙， 形成接合所述第二导电层中的所述第一间隙的第二间隙，以及将所述介电层插入所述第一和第二间隙之间。

    CIRCUIT BOARDS
    79.
    发明申请
    CIRCUIT BOARDS 审中-公开
    电路板

    公开(公告)号：US20060245172A1

    公开(公告)日：2006-11-02

    申请号：US11427737

    申请日：2006-06-29

    Applicant: Steve Van Kirk

    Inventor： Steve Van Kirk

    IPC: H05K7/12

    CPC classification number: H05K1/162 ,  H05K2201/09236 ,  H05K2201/09345

    Abstract: A circuit board may include a first conductive layer having a first interstice and a third interstice; a second conductive layer having a second interstice engaged with the first interstice, and a fourth interstice engaged with the third interstice; and a dielectric layer disposed between the first and third interstices, and the second and fourth interstices. The conductive layers may be sinuously intertwined.

    Abstract translation: 电路板可以包括具有第一间隙和第三间隙的第一导电层; 具有与第一间隙接合的第二间隙的第二导电层和与第三间隙接合的第四间隙; 以及设置在第一和第三间隙之间的介电层，以及第二和第四间隙。 导电层可以是蜿蜒交织的。

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