公开(公告)号：US07342182B2

公开(公告)日：2008-03-11

申请号：US11134363

申请日：2005-05-23

Applicant: Akiyoshi Saito

Inventor： Akiyoshi Saito

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/111 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A printed board suitable for having a LSI surface-mounted thereto and improves high-speed transfer characteristic while maintaining the circumference of a pad formed on the printed board. The pad is a connector pad consisting of a conductor pattern, and the area of the conductor pattern forming the pad is smaller than an area determined based on the circumference of the conductor pattern that forms the pad.

Abstract translation: 适合于具有LSI表面安装的LSI的印刷电路板，并且在保持形成在印刷电路板上的焊盘的周边的同时提高高速传输特性。 焊盘是由导体图案组成的连接器焊盘，并且形成焊盘的导体图案的区域小于基于形成焊盘的导体图案的周长确定的面积。

公开(公告)号：US07335571B2

公开(公告)日：2008-02-26

申请号：US10917681

申请日：2004-08-12

Applicant: Brad D. Rumsey ,  Matt E. Schwab

Inventor： Brad D. Rumsey ,  Matt E. Schwab

IPC: H01L21/76 ,  H01L21/00

CPC classification number: H01L24/49 ,  B33Y10/00 ,  B33Y80/00 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2224/85207 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0266 ,  H05K3/0008 ,  H05K3/0052 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/09918 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49222 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial are also described.

Abstract translation: 一种用于基准和引脚一指示器的方法，其利用管芯安装衬底中的单个阻焊开口来执行现有技术基准和引脚一指示器的组合功能。 还描述了使用组合销一个指示器和对准基准来制造载体衬底和制造半导体器件封装的方法。

公开(公告)号：US07307850B2

公开(公告)日：2007-12-11

申请号：US11496210

申请日：2006-07-31

Applicant: Brad D. Rumsey

Inventor： Brad D. Rumsey

IPC: H05K7/02

CPC classification number: H05K3/3452 ,  H05K2201/0989 ,  H05K2203/1178 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165

Abstract: A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.

Abstract translation: 多层电路板包括基底层，导电层和焊接掩模。 焊接层具有两组开口。 其中一个开口是通气口，露出基层以提供通风，使得气体在加工过程中可能逸出。 第二开口暴露导体层的选择区域。 多层电路板提供较少的分层出现。

公开(公告)号：US20070252286A1

公开(公告)日：2007-11-01

申请号：US11736916

申请日：2007-04-18

Applicant: Yuji Kunimoto ,  Atsunori Kajiki

Inventor： Yuji Kunimoto ,  Atsunori Kajiki

IPC: H01L23/48

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: There is provided a mounting substrate on which a semiconductor chip is mounted using a flip chip bonding, having a plurality of connection pads which are connected to the semiconductor chip, and an insulation layer formed in such a manner as to cover the connection pads partially, wherein the insulation layer includes a first insulation layer which is formed in such a manner as to correspond to a center of the semiconductor chip and a second insulation layer which is formed in such a manner as to surround the first insulation layer, and wherein the plurality of connection pads include first connection pads which are partially covered by the first insulation layer and second connection pads which are partially covered by the second insulation layer.

Abstract translation: 提供一种安装基板，其上使用倒装芯片接合安装半导体芯片，其具有连接到半导体芯片的多个连接焊盘，以及以覆盖部分连接焊盘的方式形成的绝缘层， 其中所述绝缘层包括第一绝缘层，所述第一绝缘层以与所述半导体芯片的中心相对应的方式形成;以及第二绝缘层，所述第二绝缘层以围绕所述第一绝缘层的方式形成，并且其中所述多个 连接焊盘包括由第一绝缘层部分覆盖的第一连接焊盘和被第二绝缘层部分覆盖的第二连接焊盘。

公开(公告)号：US07271484B2

公开(公告)日：2007-09-18

申请号：US10950185

申请日：2004-09-24

Applicant: Martin Reiss ,  Carsten Bender ,  Kerstin Nocke

Inventor： Martin Reiss ,  Carsten Bender ,  Kerstin Nocke

IPC: H01L23/488

CPC classification number: H05K3/3452 ,  B23K3/0638 ,  H05K3/3457 ,  H05K2201/0989 ,  H05K2201/099

Abstract: A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The solder mask has an opening that exposes a portion of the soldering pad. The opening has at least two edges that symmetrically overlie portions of the soldering pad.

Abstract translation: 可焊接装置包括衬底和覆盖衬底的焊盘。 焊接掩模覆盖基板和焊盘的部分。 焊接掩模具有露出焊盘一部分的开口。 该开口具有对称地覆盖焊盘部分的至少两个边缘。

公开(公告)号：US20070184675A1

公开(公告)日：2007-08-09

申请号：US11671729

申请日：2007-02-06

Applicant: Koji ISHIKAWA

Inventor： Koji ISHIKAWA

IPC: H05K1/00

CPC classification number: H05K3/363 ,  H05K3/3452 ,  H05K2201/09181 ,  H05K2201/09727 ,  H05K2201/0989

Abstract: A highly reliable printed circuit board which is capable of preventing a short circuit between traces from being caused by a solder bridge formed by excess solder. The printed circuit board has a solder resist covering copper foil traces formed on a substrate and the substrate, for insulation. The solder resist is formed such that exposed portions of the substrate between adjacent ones of the conductive traces each have a shape protruding in a direction of where the other printed circuit board is connected, with respect to exposed portions of the adjacent ones of the conductive traces, in a boundary between the connection part and a portion on which an insulating layer is formed.

Abstract translation: 一种高度可靠的印刷电路板，其能够防止迹线之间的短路由由多余焊料形成的焊料桥引起。 印刷电路板具有覆盖在基板和基板上形成的用于绝缘的铜箔迹线的阻焊层。 阻焊剂形成为使得相邻的导电迹线之间的基板的暴露部分相对于相邻的导电迹线的暴露部分具有沿着另一个印刷电路板连接的方向突出的形状 在连接部分和形成有绝缘层的部分之间的边界。

公开(公告)号：US07224073B2

公开(公告)日：2007-05-29

申请号：US10848649

申请日：2004-05-18

Applicant: Sung-Jin Kim

Inventor： Sung-Jin Kim

IPC: H01L23/48

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/111 ,  H05K3/3457 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611

Abstract: A substrate for solder joint is provided, including: a core layer; at least one conductive trace formed on the core layer and having a circular terminal as a pad through which a plurality of hollow portions are formed and expose predetermined portions of the core layer underneath the pad, wherein the hollow portions are arranged at equal intervals and spaced from a periphery of the circular pad; and a solder mask for covering the conductive trace and having at least one opening bordered across each of the hollow portions of the pad, such that part of the pad and part of each of the predetermined portions of the core layer are exposed via the opening, to allow a conductive element to be bonded to the exposed part of the pad and the exposed part of the predetermined portions of the core layer in the opening of the solder mask.

Abstract translation: 提供了一种用于焊接接头的基板，包括：芯层; 形成在所述芯层上的至少一个导电迹线，并且具有圆形端子作为衬垫，通过所述衬垫形成多个中空部分并且暴露所述衬垫下方的所述芯层的预定部分，其中所述中空部分以相等间隔布置并间隔开 从圆形垫的周边; 以及用于覆盖导电迹线并且具有横跨垫的每个中空部分的至少一个开口的焊料掩模，使得焊盘的一部分和芯层的每个预定部分的一部分经由开口露出， 以允许导电元件结合到焊盘的暴露部分和焊料掩模的开口中的芯层的预定部分的暴露部分。

公开(公告)号：US20070102817A1

公开(公告)日：2007-05-10

申请号：US11616164

申请日：2006-12-26

Applicant: Cheng Tay ,  Swee Cheng ,  Eng Goh

Inventor： Cheng Tay ,  Swee Cheng ,  Eng Goh

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.

Abstract translation: 提供了一种方法和装置，其涉及抵抗在球栅阵列微电子封装中的部件和基板之间的电互连中的裂纹起始和传播。 电介质限定和非介质限定的电互连的混合物减少了电互连故障的可能性，而不必控制介质限定的衬底互连比。 此外，电互连的电介质限定边缘部分远离开始点的选择性取向抵抗裂纹扩展和部件故障。

公开(公告)号：US20070096337A1

公开(公告)日：2007-05-03

申请号：US11457767

申请日：2006-07-14

Applicant: Bong Rak CHOI

Inventor： Bong Rak CHOI

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L24/28 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A void-free circuit board and a semiconductor package having the same includes a protective layer covering and protecting an electrode pattern formed on an upper surface of a substrate. The protective layer is applied around a solder ball provided on the electrode pattern except on an immediate vicinity of the solder ball to form an opening. The semiconductor package also includes at least one gap compensation part comprising a protrusion that comes in contact with an underfill material injected to the opening before the electrode pattern. The protrusion has a thickness substantially the same as that of a portion of the electrode pattern exposed in the opening. This prevents voids with air captured therein due to non-uniform capillary action during injection of the underfill material.

Abstract translation: 无空隙电路板及其半导体封装具有覆盖并保护形成在基板上表面的电极图案的保护层。 保护层围绕设置在电极图案上的焊球周围施加，除了在焊球的紧邻附近形成开口。 半导体封装还包括至少一个间隙补偿部件，其包括与在电极图案之前注入到开口处的底部填充材料接触的突起。 突出部的厚度与暴露于开口部的电极图案的部分的厚度基本相同。 这防止了在注入底部填充材料期间由于毛细作用不均匀而捕获在其中的空气的空隙。

公开(公告)号：US20070094872A1

公开(公告)日：2007-05-03

申请号：US10560849

申请日：2004-05-05

Applicant: Misao Konishi ,  Hidetsugu Namiki ,  Jyunji Shinozaki

Inventor： Misao Konishi ,  Hidetsugu Namiki ,  Jyunji Shinozaki

IPC: B32B37/00

CPC classification number: H05K13/0469 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H05K3/323 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/1105 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for mounting through an anisotropic conductive film defined as an adhesive sheet an electronic component on a printed circuit board (flexible board) provided with a wiring pattern. The anisotropic conductive film is bonded to an area of the flexible board to be mounted with the electronic component in a state where air intervening between the anisotropic conductive film and the flexible board is heated. Since the air confined between the anisotropic conductive film and the flexible board reduces in volume upon cooled down, occurrence of voids, exposure of the wiring pattern, or the like is avoided. Consequently, reliability can be enhanced without complicating the mounting.

Abstract translation: 一种在设置有布线图案的印刷电路板（柔性基板）上安装通过定义为粘合片的电子部件的各向异性导电膜的方法。 各向异性导电膜在各向异性导电膜和柔性基板之间的空气被加热的状态下与电子部件安装的柔性基板的区域接合。 由于在各向异性导电膜和柔性基板之间限制的空气在冷却时体积减小，所以避免了空隙的发生，布线图案的曝光等。 因此，可以提高可靠性，而不会使安装复杂化。