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    METHOD AND APPARATUS FOR REDUCING ELECTRICAL INTERCONNECTION FATIGUE
    3.
    发明申请
    METHOD AND APPARATUS FOR REDUCING ELECTRICAL INTERCONNECTION FATIGUE 有权
    减少电气互连疲劳的方法和装置

    公开(公告)号：US20070102817A1

    公开(公告)日：2007-05-10

    申请号：US11616164

    申请日：2006-12-26

    Applicant: Cheng Tay ,  Swee Cheng ,  Eng Goh

    Inventor： Cheng Tay ,  Swee Cheng ,  Eng Goh

    IPC: H01L23/48 ,  H01L21/44

    CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00

    Abstract: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.

    Abstract translation: 提供了一种方法和装置，其涉及抵抗在球栅阵列微电子封装中的部件和基板之间的电互连中的裂纹起始和传播。 电介质限定和非介质限定的电互连的混合物减少了电互连故障的可能性，而不必控制介质限定的衬底互连比。 此外，电互连的电介质限定边缘部分远离开始点的选择性取向抵抗裂纹扩展和部件故障。

    Socket connection test modules and methods of using the same
    4.
    发明授权
    Socket connection test modules and methods of using the same 失效
    套接字连接测试模块及使用方法

    公开(公告)号：US07208967B2

    公开(公告)日：2007-04-24

    申请号：US11223248

    申请日：2005-09-06

    Applicant: Swee Cheng Ho ,  Teik Sean Toh ,  Tzyy Haw Tan

    Inventor： Swee Cheng Ho ,  Teik Sean Toh ,  Tzyy Haw Tan

    IPC: G01R31/02

    CPC classification number: G01R31/2806 ,  G01R1/07328 ,  G01R31/048 ,  G01R31/2896

    Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.

    Abstract translation: 在本发明的实施例中给出了使用电容器测试印刷电路板（PCB）和器件插座之间的焊点连接的测试模块，系统和方法。 可以使用具有并联电容器，特别是嵌入式电容器的测试模块，通过测量电容器的总电容来测试连接迹线及其焊点连接。 本发明的实施例提出了可以与各种测试平台和测试夹具一起使用的无功功率测试，例如在线测试（ICT）和制造缺陷分析（MDA）。另外，测试模块可以与 各种插座，例如球栅阵列，钉扎网格阵列和平台网格阵列。

    Socket connection test modules and methods of using the same
    5.
    发明授权
    Socket connection test modules and methods of using the same 失效
    套接字连接测试模块及使用方法

    公开(公告)号：US07129729B2

    公开(公告)日：2006-10-31

    申请号：US11223249

    申请日：2005-09-06

    Applicant: Swee Cheng Ho ,  Teik Sean Toh ,  Tzyy Haw Tan

    Inventor： Swee Cheng Ho ,  Teik Sean Toh ,  Tzyy Haw Tan

    IPC: G01R31/02

    CPC classification number: G01R31/2806 ,  G01R1/07328 ,  G01R31/048 ,  G01R31/2896

    Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.

    Abstract translation: 在本发明的实施例中给出了使用电容器测试印刷电路板（PCB）和设备的插座之间的焊点连接的测试模块，系统和方法。 可以使用具有并联电容器，特别是嵌入式电容器的测试模块，通过测量电容器的总电容来测试连接迹线及其焊点连接。 本发明的实施例提出了可以与各种测试平台和测试夹具一起使用的无功功率测试，例如在线测试（ICT）和制造缺陷分析（MDA）。另外，测试模块可以与 各种插座，例如球栅阵列，钉扎网格阵列和平台网格阵列。

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