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    Surface mount multilayer capacitor
    71.
    发明授权
    Surface mount multilayer capacitor 有权
    表面贴装多层电容器

    公开(公告)号：US06243253B1

    公开(公告)日：2001-06-05

    申请号：US09264124

    申请日：1999-03-08

    Applicant: David A. DuPre ,  John L. Galvagni ,  Andrew P. Ritter

    Inventor： David A. DuPre ,  John L. Galvagni ,  Andrew P. Ritter

    IPC: H01G4228

    CPC classification number: H01G2/065 ,  H01G4/30 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10045 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

    Abstract: A multilayer ceramic device suitable for use in surface mount decoupling applications may have a single capacitor or a capacitor array. The device has a capacitor body defining a plurality of electrical terminals on an outer surface thereof. The terminals are interdigitated such that a respective first polarity terminal will be adjacent to a respective second polarity terminal (and vice versa). The capacitor body contains a plurality of interleaved capacitor plates in opposed and spaced apart relation. Capacitor plates of the first polarity are electrically connected to respective first polarity terminals via a plurality of lead structures. Likewise, a plurality of lead structures electrically connect capacitor plates of the second polarity to respective second polarity terminals.

    Abstract translation: 适用于表面贴装去耦应用的多层陶瓷器件可以具有单个电容器或电容器阵列。 该装置具有在其外表面上限定多个电端子的电容器主体。 端子相互交错，使得相应的第一极性端子将与相应的第二极性端子相邻（反之亦然）。 电容器主体包含相互间隔开的多个交错电容器板。 第一极性的电容器板经由多个引线结构电连接到相应的第一极性端子。 同样地，多个引线结构将第二极性的电容器板电连接到相应的第二极性端子。

    Multilayer ceramic package with low-variance embedded resistors
    72.
    发明授权
    Multilayer ceramic package with low-variance embedded resistors 失效
    具有低方位嵌入式电阻器的多层陶瓷封装

    公开(公告)号：US6100787A

    公开(公告)日：2000-08-08

    申请号：US864300

    申请日：1997-05-28

    Applicant: Rong-Fong Huang ,  Robert A. Burr

    Inventor： Rong-Fong Huang ,  Robert A. Burr

    IPC: H01C13/02 ,  H01L23/538 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/46 ,  H01C7/18

    CPC classification number: H01C13/02 ,  H01L23/5383 ,  H05K1/167 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/09672 ,  H05K2201/10045 ,  H05K2203/1453 ,  H05K3/4611 ,  H05K3/4629

    Abstract: A multilayer electronic component (200) is provided. The component includes a substrate package assembly (202) with a set of stacked insulated sheets of a dielectric ceramic material (204, 206, 208, 210, 212). Also included are a set of embedded resistors (214), each of the embedded resistors including an electrical input port pad (216) and an electrical output port pad (218) provided in layers between the set of stacked insulated sheets. Each of the insulated sheets has a trough (220) of a predetermined length aligned between and transverse to the electrical input port pad (216) and the electrical output port pad (218). The trough (220) reduces the resistance value variability in the multilayer electronic component (200). The trough (220) is substantially filled with a resistive paste material and an internal circuit (222) connects the embedded resistors inside the substrate package assembly (202). A method of forming the substrate package assembly (202) is also provided.

    Abstract translation: 提供了一种多层电子部件（200）。 该组件包括具有介电陶瓷材料（204,206,208,210,212）的一组堆叠的绝缘片的衬底封装组件（202）。 还包括一组嵌入式电阻器（214），每个嵌入式电阻器包括设置在该组堆叠绝缘片材之间的层中的电输入端口衬垫（216）和电输出端口衬垫（218）。 每个绝缘片具有在电输入端口衬垫（216）和电输出端口衬垫（218）之间并且横向于电输入端口衬垫（216）并且横向于电输入端口衬垫（216）的预定长度的槽（220）。 槽（220）降低了多层电子部件（200）中的电阻值变化。 槽（220）基本上被电阻浆料材料填充，并且内部电路（222）连接衬底封装组件（202）内的嵌入式电阻器。 还提供了一种形成衬底封装组件（202）的方法。

    Thermally matched electronic components
    74.
    发明授权
    Thermally matched electronic components 失效
    热电偶配件

    公开(公告)号：US5506754A

    公开(公告)日：1996-04-09

    申请号：US267535

    申请日：1994-06-29

    Applicant: Mark Brooks ,  Gary Seibel

    Inventor： Mark Brooks ,  Gary Seibel

    IPC: H05K1/02 ,  H05K1/14 ,  H05K3/28 ,  H05K3/34 ,  H05K3/36 ,  H05K7/20

    CPC classification number: H05K3/368 ,  H05K1/141 ,  H05K3/3442 ,  H05K1/023 ,  H05K2201/068 ,  H05K2201/09181 ,  H05K2201/09572 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10636 ,  H05K2201/10984 ,  H05K2201/10992 ,  H05K3/28 ,  Y02P70/611 ,  Y02P70/613

    Abstract: Discrete circuit devices constructed on a component substrate thermally matched to the supporting substrate of a higher level circuit assembly. Upon securing each component to the supporting substrate of a higher level circuit assembly, a connection subject to reduced thermal stress is obtained. In the construction of an exemplary surface mount, hybrid component containing resistors and capacitors, a component substrate of a polyimide impregnated material is populated with a repeating matrix of chip capacitors and chip resistors, which are adhesively bound and soldered to selected termination pads containing high temperature solder filled through vias. The substrate is epoxy encapsulated and then diced at selected ones of the through vias into multiple components. Each thermally matched component is resoldered at the separated vias to obtain surface mount terminations. Portions of the vias may be exposed through the component sidewall to permit circuit test. Other, exemplary thermally matched components, constructed of multi-layer resin or ceramic substrates are also disclosed and wherein external termination pads are concentrated to the center of the component. Alternative, thermally matched transmission lines and resistor network circuits are also disclosed.

    Abstract translation: 构造在与上层电路组件的支撑衬底热匹配的部件衬底上的分立电路器件。 在将每个部件固定到较高级别的电路组件的支撑基板上时，获得了受热应力降低的连接。 在示例性表面安装的构造中，包含电阻器和电容器的混合元件，聚酰亚胺浸渍材料的部件衬底填充有片状电容器和片状电阻器的重复矩阵，其被粘合地结合并焊接到包含高温的选定的端接焊盘 焊料填充通孔。 衬底被环氧树脂封装，然后在选择的通孔中切成多个成分。 每个热匹配组件在分离的通孔处被转化，以获得表面贴装终端。 通孔的一部分可以通过部件侧壁暴露以允许电路测试。 还公开了由多层树脂或陶瓷基板构成的其它示例性热匹配部件，并且其中外部端接焊盘被集中到部件的中心。 还公开了替代的热匹配传输线路和电阻器网络电路。

    CIRCUIT BOARD ARCHITECTURE SUPPORTING MULTIPLE COMPONENT SUPPLIERS
    76.
    发明公开
    CIRCUIT BOARD ARCHITECTURE SUPPORTING MULTIPLE COMPONENT SUPPLIERS 审中-公开

    公开(公告)号：US20230345627A1

    公开(公告)日：2023-10-26

    申请号：US17729801

    申请日：2022-04-26

    Applicant: Microsoft Technology Licensing, LLC

    Inventor： Fatemeh ZOLFAGHAR ,  Rich Tat AN ,  Bhret Robert GRAYDON

    IPC: H05K1/02

    CPC classification number: H05K1/0262 ,  H05K2201/10045

    Abstract: Techniques and systems for electronic circuit board design is provided herein. An example apparatus comprises an input structure that couples an input voltage node on a circuit board to input nodes of more than one voltage regulator circuit, wherein at least controller footprints differ among each of the more than one voltage regulator circuit. The apparatus further comprises a shared structure that couples switch nodes of the more than one voltage regulator circuit to a first terminal of an inductor footprint common to the more than one voltage regulator circuit, and an output structure that couples a second terminal of the inductor footprint to an output voltage node.

    Surface mount devices with minimum lead inductance and methods of manufacturing the same
    80.
    发明授权
    Surface mount devices with minimum lead inductance and methods of manufacturing the same 有权
    具有最小引线电感的表面贴装器件及其制造方法

    公开(公告)号：US08493744B2

    公开(公告)日：2013-07-23

    申请号：US11732543

    申请日：2007-04-03

    Applicant: Qiang Richard Chen

    Inventor： Qiang Richard Chen

    IPC: H05K7/00

    CPC classification number: H05K3/3442 ,  H01L27/016 ,  H01L27/13 ,  H05K1/16 ,  H05K3/366 ,  H05K3/403 ,  H05K2201/0317 ,  H05K2201/09954 ,  H05K2201/10045 ,  Y02P70/613

    Abstract: A device according to various aspects of the present invention generally includes a surface mount device having a top side, a bottom side, a plurality of sidewalls, and a circuit comprising one or more layers. The device includes a first conductive surface covering a portion of one of the sidewalls for providing an input to the circuit, a second conductive surface covering a portion of one of the sidewalls for providing an output from the circuit, and a third conductive surface covering a portion of one of the sidewalls for providing an electrical ground to the circuit. When the surface mount device is mounted to a provided mounting surface, at least one layer of the circuit is orthogonal to the provided mounting surface.

    Abstract translation: 根据本发明的各个方面的装置通常包括具有顶侧，底侧，多个侧壁和包括一个或多个层的电路的表面安装装置。 所述装置包括覆盖所述侧壁之一的一部分以提供所述电路的输入的第一导电表面，覆盖所述侧壁之一的一部分以提供来自所述电路的输出的第二导电表面，以及覆盖所述侧壁的第三导电表面 所述侧壁之一的一部分用于向所述电路提供电接地。 当表面安装装置安装到所提供的安装表面时，电路的至少一层与所提供的安装表面正交。

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