公开(公告)号：US09743530B2

公开(公告)日：2017-08-22

申请号：US14798538

申请日：2015-07-14

Applicant: Texas Instruments Incorporated

Inventor： Chikara Azuma

IPC: H05K1/18 ,  H05K3/30 ,  H01G2/06 ,  H01G4/06 ,  H01G4/30 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/16 ,  H05K3/42 ,  H01L23/00 ,  H05K3/46

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of electrically conductive material layers comprise first and second patterns. The first pattern comprises at least a first pair of overlaying areas free of the electrically conductive material, and the second pattern comprises at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. The plurality of electrically conductive material layers are electrically isolated from one another by the dielectric layers.

公开(公告)号：US20150255216A1

公开(公告)日：2015-09-10

申请号：US14201469

申请日：2014-03-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Shree Krishna Pandey ,  Irfan Khan ,  Nazanin Darbanian ,  John David Eaton

IPC: H01G4/30 ,  H05K1/18 ,  H01L49/02

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/242 ,  H01G4/35 ,  H05K1/0231 ,  H05K1/182 ,  H05K2201/09345 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

Abstract: A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.

Abstract translation: 具有低等效串联电感的电容器包括与连接在一起的交替的电极层并联布置的多个电极层，以形成电容器的两个电极。 第一组电极层通过外壁连接。 第二组电极层通过中心柱连接。 电容器上的端子可以在表面上间隔开，使得当电容器安装在印刷电路板或集成电路封装上时可以方便地布线信号。 端子可以包括在电容器的相对表面上以提供堆叠。 此外，其中一个端子基本上围绕另一个端子并且可以提供电磁屏蔽。

公开(公告)号：US20120081832A1

公开(公告)日：2012-04-05

申请号：US13305181

申请日：2011-11-28

Applicant: Azuma Chikara

Inventor： Azuma Chikara

IPC: H01G4/30

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Abstract translation: 电容性前体包括层叠在基板上的导电材料层。 导电层提供第一和第二图案。 这些图案各自包括没有导电材料的覆盖区域。 第一对区域覆盖具有导电材料的第二图案的区域，并且第二对区域覆盖具有导电材料的第一图案的区域。 电介质层介于相邻的导电材料层之间用于电隔离。 一个或多个电容性前体可以掉落到板上或者在组装封装的半导体器件期间并且具有与其相应的板连接在一起的导电层，以在组装期间使用传统的组装步骤形成电容器。

公开(公告)号：US20110183162A1

公开(公告)日：2011-07-28

申请号：US13080570

申请日：2011-04-05

Applicant: Daniel A. Chandler ,  Matthew P. Galla

Inventor： Daniel A. Chandler ,  Matthew P. Galla

IPC: H01M10/42 ,  H01C1/01

CPC classification number: H01C1/1406 ,  H01C1/144 ,  H01C7/02 ,  H05K3/328 ,  H05K2201/10492 ,  H05K2201/10643

Abstract: A surface mount circuit protection device includes a laminar PTC resistive element having first and second major surfaces and a thickness therebetween. A first electrode layer substantially coextensive the first surface is formed of a first metal material of a type adapted to be soldered to a printed circuit substrate. A second electrode layer formed at the second major surface includes structure forming or defining a weld plate. The metal weld plate has a thermal mass and thickness capable of withstanding resistance micro spot welding of a strap interconnect without significant resultant damage to the device. The device is preferably surface mounted to a printed circuit board assembly forming a battery protection circuit connected to a battery/cell by battery strap interconnects, wherein one of the battery strap interconnects is micro spot welded to the weld plate of the device.

Abstract translation: 表面安装电路保护装置包括具有第一和第二主表面的层状PTC电阻元件和它们之间的厚度。 基本上共同延伸第一表面的第一电极层由适于焊接到印刷电路基板的第一金属材料形成。 形成在第二主表面处的第二电极层包括形成或限定焊接板的结构。 金属焊接板具有热质量和厚度，能够耐受带状互连的电阻微点焊，而不会对器件造成严重的损害。 该装置优选地表面安装到印刷电路板组件，其形成通过电池带互连连接到电池/电池的电池保护电路，其中电池带互连中的一个被微点焊接到装置的焊接板。

公开(公告)号：US20110179642A1

公开(公告)日：2011-07-28

申请号：US13064542

申请日：2011-03-30

Applicant: Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

Inventor： Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

IPC: H05K3/30

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/0236 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: A method of embedding a chip capacitor in a printed circuit board including a first conductive layer and a dielectric layer placed on the first conductive layer includes removing the dielectric layer to form a cavity exposing the first conductive layer; seating a chip capacitor in the cavity; filling a filled material at a space excluding a space occupied by the chip capacitor in the cavity; forming a via penetrating the filled material and being connected to the chip capacitor; and stacking a conductive material to constitute a second conductive layer in surfaces of the via and the dielectric layer and in an surface of the filled material filled in the cavity.

Abstract translation: 将片状电容器嵌入到包括放置在第一导电层上的第一导电层和介电层的印刷电路板中的方法包括去除电介质层以形成露出第一导电层的空腔; 将片状电容器放置在空腔中; 在不包括空腔中的片状电容器占据的空间的空间填充填充材料; 形成穿过填充材料并连接到片式电容器的通孔; 并且在通孔和电介质层的表面和填充在空腔中的填充材料的表面中堆叠导电材料以构成第二导电层。

公开(公告)号：US20100165525A1

公开(公告)日：2010-07-01

申请号：US12720110

申请日：2010-03-09

Applicant: Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  William F. Wiedemann ,  Thomas J. Obenhuber ,  Inessa Obenhuber

Inventor： Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  William F. Wiedemann ,  Thomas J. Obenhuber ,  Inessa Obenhuber

IPC: H02H9/06 ,  H02H9/04

CPC classification number: H01C7/003 ,  H01C13/02 ,  H01G4/33 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/0246 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/10643 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.

Abstract translation: 公开了适用于在电子互连衬底内，互连衬底和电子部件之间或IC封装内的垂直互连模式下放置和使用的薄型离散电子部件结构。

公开(公告)号：US07701323B1

公开(公告)日：2010-04-20

申请号：US10857830

申请日：2004-06-01

Applicant: Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  William F. Wiedemann ,  Thomas J. Obenhuber ,  Inessa Obenhuber, legal representative

Inventor： Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  William F. Wiedemann ,  Thomas J. Obenhuber

IPC: H01C1/012

CPC classification number: H01C7/003 ,  H01C13/02 ,  H01G4/33 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/0246 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/10643 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.

Abstract translation: 公开了适用于在电子互连衬底内，互连衬底和电子部件之间或IC封装内的垂直互连模式下放置和使用的薄型离散电子部件结构。

公开(公告)号：US20100055943A1

公开(公告)日：2010-03-04

申请号：US12260454

申请日：2008-10-29

Applicant: Jeong Hyun PARK

Inventor： Jeong Hyun PARK

IPC: H01R12/00

CPC classification number: H05K1/023 ,  H01L2224/48227 ,  H01L2924/1815 ,  H01L2924/19105 ,  H05K1/182 ,  H05K1/183 ,  H05K2201/10159 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

Abstract: A circuit board for a memory card includes a circuit board body having a chip region and a peripheral region defined along a periphery of the chip region. The circuit board body includes circuit lines and element mounting parts which provide receiving spaces in the peripheral region. First connection pads are located in the peripheral region and are connected to the circuit lines. Second connection pads are located adjacent to the element mounting parts and are connected to the circuit lines. Passive elements are mounted in the element mounting parts so that at least a portion of the passive elements are formed within the circuit board body, and the passive elements are electrically connected to the second connection pads.

Abstract translation: 用于存储卡的电路板包括具有芯片区域和沿着芯片区域的外围限定的周边区域的电路板主体。 电路板主体包括在外围区域提供接收空间的电路线和元件安装部分。 第一连接焊盘位于外围区域中并连接到电路线。 第二连接垫位于元件安装部分附近并连接到电路线。 无源元件安装在元件安装部分中，使得至少一部分无源元件形成在电路板主体内，并且无源元件电连接到第二连接焊盘。

公开(公告)号：US20090215231A1

公开(公告)日：2009-08-27

申请号：US12366140

申请日：2009-02-05

Applicant: Osamu INOUE

Inventor： Osamu INOUE

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/06 ,  H05K3/061 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2203/1152 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In a method of manufacturing an electronic component built-in substrate of the present invention, a mounted body including a first insulating layer, a stopper metal layer formed under the first insulating layer of a portion corresponding to a component mounting region and a second insulating layer formed on a lower surface of the first insulating layer and covering the stopper metal layer is prepared, and a concave portion is obtained by penetration-processing a portion of the first insulating layer, which corresponds to the component mounting region to form an opening portion, while using the stopper metal layer as a stopper. Also, the stopper metal layer in the concave portion is removed, then an electronic component is mounted on the concave portion, and then a third insulating layer is formed on the electronic component.

Abstract translation: 在本发明的电子部件内置基板的制造方法中，具有第一绝缘层，形成在对应于部件安装区域的部分的第一绝缘层下方的止动金属层的安装体和第二绝缘层 形成在第一绝缘层的下表面上并覆盖止动金属层，并且通过对与元件安装区域相对应的第一绝缘层的一部分进行穿透处理而形成凹部以形成开口部， 同时使用塞子金属层作为塞子。 此外，去除凹部中的止动金属层，然后将电子部件安装在凹部上，然后在电子部件上形成第三绝缘层。

公开(公告)号：US20090085691A1

公开(公告)日：2009-04-02

申请号：US12007793

申请日：2008-01-15

Applicant: Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

Inventor： Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

IPC: H03H7/00 ,  H05K3/30

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/0236 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: A printed circuit board having an embedded chip capacitor is disclosed. According to an embodiment of the present invention, a printed circuit board having an embedded chip capacitor can include a first conductive layer; a second conductive layer, placed away from the first conductive layer; a chip capacitor, placed between the first conductive layer and the second conductive layer and having a second electrode, connected to the second conductive layer; and a via, connecting the first conductive layer to a first electrode of the chip capacitor. With the present invention, a problem mixed signals can be solved in the printed circuit board including an analog circuit and a digital circuit board by using the chip capacitor embedded in the printed circuit board as an electromagnetic bandgap structure. Here, various electrical devices or elements are mounted in the printed circuit board.

Abstract translation: 公开了一种具有嵌入式芯片电容器的印刷电路板。 根据本发明的实施例，具有嵌入式芯片电容器的印刷电路板可以包括第一导电层; 远离所述第一导电层放置的第二导电层; 芯片电容器，放置在第一导电层和第二导电层之间，并具有连接到第二导电层的第二电极; 以及将所述第一导电层连接到所述芯片电容器的第一电极的通孔。 利用本发明，通过使用嵌入在印刷电路板中的片状电容器作为电磁带隙结构，可以在包括模拟电路和数字电路板的印刷电路板中解决问题混合信号。 这里，各种电气设备或元件安装在印刷电路板中。