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    CASCADING EXECUTION OF ATOMIC OPERATIONS
    85.
    发明公开
    CASCADING EXECUTION OF ATOMIC OPERATIONS 审中-公开

    公开(公告)号：US20230205696A1

    公开(公告)日：2023-06-29

    申请号：US17563869

    申请日：2021-12-28

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： JIMSHED MIRZA ,  MARK FOWLER

    IPC: G06F12/084 ,  G06F12/0895 ,  G06F12/0811 ,  G06F9/30

    CPC classification number: G06F12/084 ,  G06F12/0895 ,  G06F12/0811 ,  G06F9/3009

    Abstract: Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

    PROCESSING UNIT RESET BY A VIRTUAL FUNCTION
    86.
    发明公开
    PROCESSING UNIT RESET BY A VIRTUAL FUNCTION 审中-公开

    公开(公告)号：US20230205287A1

    公开(公告)日：2023-06-29

    申请号：US17564139

    申请日：2021-12-28

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： Yinan JIANG

    IPC: G06F1/24 ,  G06F9/455 ,  G06F11/14

    CPC classification number: G06F1/24 ,  G06F9/45558 ,  G06F11/1484 ,  G06F2009/45575 ,  G06F2201/815

    Abstract: A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.

    FAST DROOP DETECTION CIRCUIT
    88.
    发明公开
    FAST DROOP DETECTION CIRCUIT 审中-公开

    公开(公告)号：US20230195191A1

    公开(公告)日：2023-06-22

    申请号：US17559111

    申请日：2021-12-22

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Kaushik Mazumdar ,  Miguel Rodriguez ,  Mikhail Rodionov ,  Stephen Victor Kosonocky

    IPC: G06F1/28 ,  H03K19/20 ,  H03K5/24 ,  H03K3/037

    CPC classification number: G06F1/28 ,  H03K19/20 ,  H03K5/2472 ,  H03K3/037

    Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.

    DDR memory error recovery
    89.
    发明授权
    DDR memory error recovery 有权

    公开(公告)号：US11675659B2

    公开(公告)日：2023-06-13

    申请号：US15375076

    申请日：2016-12-09

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： James R. Magro ,  Ruihua Peng ,  Anthony Asaro ,  Kedarnath Balakrishnan ,  Scott P. Murphy ,  YuBin Yao

    IPC: G06F11/10 ,  G06F13/16 ,  G06F13/40

    CPC classification number: G06F11/1016 ,  G06F11/10 ,  G06F13/1626 ,  G06F13/4022

    Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

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