公开(公告)号：US20040003367A1

公开(公告)日：2004-01-01

申请号：US10185177

申请日：2002-06-28

Applicant: Cray Inc.

Inventor： Robert J. Lutz

IPC: G06F017/50

CPC classification number: G06F17/5045

Abstract: A method of instantiating a leaf cell having various connections and designed to be called using a fixed syntax includes defining a template syntax different from the fixed syntax, setting default values for connections not designated by the template syntax, and mapping the template syntax to a hardware design language. The description of the leaf cell has values for the designated connections and non-designated connections. The non-designated connections have the default values. Another method includes instantiating a leaf cell using a first template syntax or a second template syntax. The second template syntax instantiates the same leaf cell as the first template syntax or the fixed syntax. In addition, more than one leaf cell, also known as a branch, can be instantiated using the template syntax. Articles of manufacture that include a computer readable media having instructions thereon for causing a suitably programmed system to execute one or more of the above methods of instantiating a leaf cell or leaf cells are also discussed.

公开(公告)号：US20030079090A1

公开(公告)日：2003-04-24

申请号：US10045591

申请日：2001-10-24

Applicant: Cray Inc.

Inventor： James R. Kohn ,  Robert J. Baird

IPC: G06F012/00

CPC classification number: G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0808

Abstract: A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the first memory, wherein the first cache caches data accessed by the first processor from the first memory, wherein the first processor executes: a resource-synchronization instruction, an instruction that enables a cache-invalidate function to be performed upon execution of the resource-synchronization instruction, and an instruction that disables the cache-invalidate function from being performed upon execution of the resource-synchronization instruction.

Abstract translation: 一种用于选择性地启用对诸如测试和设置的资源同步指令的高速缓存无效功能补充的方法和系统。 一些实施例包括第一处理器，第一存储器，第一处理器和第一存储器之间的至少第一高速缓存，其中第一高速缓存从第一存储器缓存由第一处理器访问的数据，其中第一处理器执行： 同步指令，执行资源同步指令时执行高速缓存无效功能的指令，以及执行资源同步指令时禁止高速缓存无效功能的指令。

公开(公告)号：US12112261B2

公开(公告)日：2024-10-08

申请号：US16714347

申请日：2019-12-13

Applicant: Cray Inc.

Inventor： Samuel H. Partee ,  Benjamin J. Robbins ,  Michael F. Ringenburg

IPC: G06N3/08 ,  G01W1/02 ,  G06N20/20

CPC classification number: G06N3/08 ,  G01W1/02 ,  G06N20/20

Abstract: One embodiment can provide a method and system for tuning parameters of a numerical model of a physical system. During operation, the system can obtain, using a machine-learning technique, a parameter-transform model for mapping parameters of the numerical model at a first resolution to parameters of the numerical model at a second resolution, the second resolution being higher than the first resolution. The system can perform a parameter-tuning operation on the numerical model at a first resolution to obtain a first set of tuned parameters and apply the parameter-transform model on the first set of tuned parameters to obtain a second set of tuned parameters at a second resolution. The system can then generate behavior information associated with the physical system by running the numerical model at the second resolution using the second set of tuned parameters.

公开(公告)号：US11009934B2

公开(公告)日：2021-05-18

申请号：US16136218

申请日：2018-09-19

Applicant: Cray Inc.

Inventor： Josh Williams ,  Steve Martin ,  Clark Snyder ,  David Rush ,  Matthew Kappel

IPC: G06F1/00 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/50

Abstract: To eliminate the adverse effects of power swings in a large scale computing system during the life cycle of an application or job, control of several operating characteristics for the collective group of processors is provided. By providing certain levels of coordination for the many processors utilized in large scale computing systems, significant and abrupt changes in power needs can be avoided. In certain circumstances, this may involve limiting the transition between several C-States of the processors involved and the overall power transitions for a large scale system are not detrimental and do not create issues for the data center or local power utility. Some cases will require stepped transitions between C-States, while other cases will include both stepped and modulated transitions. Other cases will incorporate random wait times at the various transitions in order to spread the power consumption involved. In yet further circumstances the C-States can be pinned to a specific setting, thus avoiding transitions caused by C-State transitions. To deal with further issues, the processor P-States can also be overridden.

公开(公告)号：US10884859B2

公开(公告)日：2021-01-05

申请号：US16385448

申请日：2019-04-16

Applicant: Cray Inc.

Inventor： Laurence S. Kaplan ,  Preston Pengra Briggs, III ,  Miles Arthur Ohlrich ,  Willard Huston Leslie

IPC: G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G06F3/06 ,  G06F11/16 ,  G06F11/08

Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.

公开(公告)号：US20200375025A1

公开(公告)日：2020-11-26

申请号：US16880944

申请日：2020-05-21

Applicant: Cray Inc.

Inventor： Hyunjun Kim ,  Andrew J. Becker ,  Paul Taylor Wildes ,  Gregory E. Scott

IPC: H05K1/02 ,  H01P3/08

Abstract: One embodiment provides a printed circuit board (PCB). The PCB can include one or more metal layers and at least a pair of differential transmission lines. The pair of differential transmission lines can include a first transmission line and a second transmission line. The first transmission line can include a plurality of timing-skew-compensation structures, and a respective timing-skew-compensation structure of the first transmission line or a corresponding segment of the second transmission line adjacent to the timing-skew-compensation structure has a non-uniform width.

公开(公告)号：US10782749B2

公开(公告)日：2020-09-22

申请号：US16156732

申请日：2018-10-10

Applicant: Cray Inc.

Inventor： Wendell Lengefeld ,  Abhishek Mehta ,  William Mark Megarity ,  Mark E. Steinke ,  Benjamin Colin Heshmat

IPC: H05K7/20 ,  H05K7/14 ,  G06F1/20 ,  G06F1/18

Abstract: A circuit assembly is provided which makes efficient us of space provided on a main board having a CPU and a supporting board which is designed to have a network interface chip (NIC). The circuit assembly further has a cooling plate situated between the two boards, which is optimized to provide efficient cooling operations. The circuit assembly is part of a blade, which includes a housing to contain and support all necessary components. The space within the blade housing is efficiently used, so that processing, communication and cooling operations are all optimized.

公开(公告)号：US10698813B2

公开(公告)日：2020-06-30

申请号：US16034216

申请日：2018-07-12

Applicant: Cray, Inc.

Inventor： Heidi Lynn Poxon ,  William Homer ,  David W. Oehmke ,  Luiz DeRose ,  Clayton D. Andreasen ,  Sanyam Mehta

IPC: G06F12/02 ,  G06F12/08 ,  G06F8/41 ,  G06F12/0871

Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.

公开(公告)号：US10595394B1

公开(公告)日：2020-03-17

申请号：US16407721

申请日：2019-05-09

Applicant: Cray Inc.

Inventor： Hyunjun Kim ,  Paul Wildes ,  Andy Becker ,  Shawn Utz

IPC: H05K1/02 ,  H05K1/11

Abstract: A printed circuit board includes additional stitching vias placed at strategic location within a connection matrix, which provides additional isolation and further accommodates high-speed communication capabilities. The stitching vias have a variable length or depth, depending on related structures within the circuit board, so as to avoid any interference with underlining escape routing, or alternative signal transmission structures. More specifically, these stitching vias help to eliminate cross-talk in the via field caused by the close proximity of signal carrying structures. Further, differential signal communication is better accommodated based upon this reduction in cross-talk.

公开(公告)号：US10588246B2

公开(公告)日：2020-03-10

申请号：US15213131

申请日：2016-07-18

Applicant: Cray Inc.

Inventor： Douglas P. Kelley ,  Wade J. Doll ,  Alexander I. Yatskov

IPC: H05K7/20

Abstract: Computer systems and associated methods for cooling computer components are disclosed herein. One embodiment of a computer system includes a computer cabinet having an air inlet spaced apart from an air outlet. The computer system also includes heat exchangers positioned in the computer cabinet, and a heat removal system in fluid communication with the heat exchangers. The computer system additionally includes at least one sensor for monitoring heat transfer between the computer cabinet and the room. The computer system further includes a control system operatively coupled to the at least one sensor, the control system including a computer-readable medium holding instructions for determining whether heat transfer between the computer cabinet and the room is balanced based on information from the sensor, and if not, adjusting a parameter to balance the heat transfer.