公开(公告)号：US09397151B1

公开(公告)日：2016-07-19

申请号：US14136040

申请日：2013-12-20

Applicant: Integrated Device Technology, Inc.

Inventor： Kenneth L. Astrof ,  Robert A. Gubser ,  Ajay Kumar Ghai ,  Viresh Piyush Patel ,  Jitesh Shah

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F27/00 ,  H01L21/50 ,  H01L23/10 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/552 ,  H01L23/645 ,  H01L2224/16225

Abstract: A packaged integrated circuit includes an integrated circuit substrate and a cap bonded to a surface of the integrated circuit substrate. The cap has a recess therein that is at least partially lined with at least one segment of an inductor. This inductor may be electrically coupled to an electrical component within the integrated circuit substrate. In some embodiments, the inductor is patterned to extend along a sidewall and interior top surface of the recess, which extends opposite the integrated circuit substrate. The inductor may include a plurality of arcuate-shaped segments and may be patterned to be symmetric about a center-tapped portion thereof. The cap may also include a magnetic material therein that increases an effective inductance of the inductor relative to an otherwise equivalent cap and inductor combination that is devoid of the magnetic material.

Abstract translation: 封装的集成电路包括集成电路基板和结合到集成电路基板的表面的盖。 盖子在其中具有至少部分地衬有电感器的至少一个部分的凹部。 该电感器可以电耦合到集成电路基板内的电气部件。 在一些实施例中，电感器被图案化以沿着与集成电路基板相对延伸的凹部的侧壁和内部顶表面延伸。 电感器可以包括多个弧形段，并且可以被图案化成关于其中心抽头部分对称。 盖子还可以包括其中的磁性材料，其相对于没有磁性材料的否则相当的盖和电感器组合增加了电感器的有效电感。

公开(公告)号：US09369270B1

公开(公告)日：2016-06-14

申请号：US14212598

申请日：2014-03-14

Applicant: Integrated Device Technology, Inc.

Inventor： Menno Spijker

IPC: H03D3/24 ,  H04L7/033 ,  H03L7/07

CPC classification number: H04L7/0331 ,  H03L7/07 ,  H04J3/0641 ,  H04J3/0658 ,  H04J3/0667

Abstract: A Synchronous Ethernet (SyncE) network device includes a pair of phase-locked loops including a first phase-locked loop responsive to a SyncE input clock and a second phase-locked loop coupled to the first phase-locked loop. The second phase-locked loop is configured to be simultaneously lockable to both the SyncE input clock via the first phase-locked loop and an IEEE 1588 packet stream, during a locked mode of operation, and also lockable to the SyncE input clock during a holdover mode of operation which is triggered in response to a failure of the IEEE 1588 packet stream.

Abstract translation: 同步以太网（SyncE）网络设备包括一对锁相环，包括响应于SyncE输入时钟的第一锁相环和耦合到第一锁相环的第二锁相环。 第二锁相环被配置为在锁定操作模式期间通过第一锁相环和IEEE1588分组流同时锁定SyncE输入时钟，并且还可以在保持期间锁定到SyncE输入时钟 响应于IEEE 1588分组流的故障触发的操作模式。

公开(公告)号：US09306537B1

公开(公告)日：2016-04-05

申请号：US14586508

申请日：2014-12-30

Applicant: Integrated Device Technology, Inc.

Inventor： Robert A. Gubser ,  Ajay Kumar Ghai ,  Viresh Piyush Patel

IPC: H03B5/36 ,  H03B1/02 ,  H03H9/17 ,  H01L41/053 ,  H01L41/047

CPC classification number: H03H9/17 ,  H03B1/02 ,  H03H9/0547 ,  H03H9/1021

Abstract: An integrated circuit device includes an integrated circuit substrate having a two piece package thereon. The package has a hermetically sealed cavity therein and a crystal resonator within the cavity. The crystal resonator includes at least one electrode electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package may include a material selected from a group consisting of glass and ceramics. The crystal resonator includes a crystal blank and first and second electrodes on first and second opposing sides of the crystal blank. The package includes a base having a recess therein and a cap hermetically sealed to the base. The cap includes first and second electrical traces thereon, which are electrically connected to the first and second electrodes of the crystal resonator.

Abstract translation: 集成电路器件包括其上具有两片封装的集成电路衬底。 该封装在其中具有气密密封腔，并且在腔内具有晶体谐振器。 晶体谐振器包括至少一个电极，其通过导电通孔电连接到集成电路基板的一部分，导电通孔至少部分延伸穿过封装。 包装可以包括从由玻璃和陶瓷组成的组中选择的材料。 晶体谐振器包括晶体坯料和晶体坯料的第一和第二相对侧上的第一和第二电极。 该包装包括其中具有凹部的底座和密封到底座的盖。 盖包括其上的第一和第二电迹线，其电连接到晶体谐振器的第一和第二电极。

公开(公告)号：US09270280B1

公开(公告)日：2016-02-23

申请号：US14136012

申请日：2013-12-20

Applicant: Integrated Device Technology, Inc.

Inventor： Mihai A. Margarit ,  Mohamed AH. Mostafa

IPC: H03K21/00 ,  H03K23/00 ,  H03K23/70 ,  H03K21/38 ,  H03K21/02 ,  H03K23/68

CPC classification number: H03K23/70 ,  H03K21/00 ,  H03K21/023 ,  H03K21/38 ,  H03K23/00 ,  H03K23/667 ,  H03K23/68

Abstract: A fractional-N frequency divider includes a half-integer frequency divider and a duty cycle adjustment circuit. The half-integer frequency divider includes a multi-modulus divider containing a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal, and a phase control circuit configured support half-integer frequency division by the multi-modulus divider, by providing an input terminal of the multi-modulus divider with a periodically phase-flipped input signal having a first frequency. The duty-cycle adjustment circuit is configured to generate a divider output signal with a 50% duty cycle in response to a periodic signal generated by the half-integer frequency divider.

Abstract translation: 分数N分频器包括半整数分频​​器和占空比调整电路。 半整数分频​​器包括多模除法器，其包含对多位模数控制信号进行响应的div2 / 3单元的级联链，以及配置为支持多位模数控制信号的半整数分频​​的相位控制电路， 模数分频器，通过为多模式分配器的输入端提供具有第一频率的周期性相位反转的输入信号。 占空比调整电路被配置为响应于半整数分频​​器产生的周期信号而产生具有50％占空比的分频器输出信号。

公开(公告)号：US09264027B1

公开(公告)日：2016-02-16

申请号：US14190890

申请日：2014-02-26

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： Amit Majumder

IPC: H03K3/011 ,  H03H11/26 ,  H03K5/14 ,  G05F3/16

CPC classification number: H03K5/14 ,  G05F3/16

Abstract: A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.

Abstract translation: 已经公开了一个过程补偿延迟。 在一个实现中，延迟主要基于电子迁移率。

公开(公告)号：US20160013885A1

公开(公告)日：2016-01-14

申请号：US14327333

申请日：2014-07-09

Applicant: Integrated Device Technology, Inc.

Inventor： Barry Everett Wood

IPC: H04L1/00 ,  H04L12/947 ,  H04L12/26 ,  H04L12/801

CPC classification number: H04L1/004 ,  H04L1/0061 ,  H04L1/0083 ,  H04L1/1607 ,  H04L43/0847 ,  H04L49/25

Abstract: The present invention provides a RapidIO device that includes a switch fabric and a port coupled to the switch fabric. The port is configured to establish a LP-Serial link with RapidIO endpoints, add packet headers having the same acknowledgement identifier to a plurality of contiguous packets and generate a link cyclical redundancy check value for the plurality of contiguous packets having the same acknowledgement identifier, the link cyclical redundancy check code computed to include the value of an acknowledgement identifier header. The port is configured to sequentially output the plurality of packets having the same acknowledgement identifier on the LP-Serial link. In addition, methods are disclosed for formatting bit streams in a RapidIO based communication system and communicating RapidIO packets.

Abstract translation: 本发明提供了一种RapidIO设备，其包括交换结构和耦合到交换结构的端口。 端口被配置为与RapidIO端点建立LP串行链路，将具有相同的确认标识符的分组报头添加到多个连续分组，并为具有相同的确认标识符的多个连续分组生成链路循环冗余校验值， 计算的链路循环冗余校验码包括确认标识符头的值。 端口被配置为在LP串行链路上顺序地输出具有相同的确认标识符的多个分组。 另外，公开了用于在基于RapidIO的通信系统中格式化比特流并传送RapidIO分组的方法。

公开(公告)号：US09154147B2

公开(公告)日：2015-10-06

申请号：US14209848

申请日：2014-03-13

Applicant: Integrated Device Technology, Inc.

Inventor： Arnaud Biallais ,  Fatima Ghanem

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/08 ,  H03M1/10

CPC classification number: H03M1/0609 ,  H03M1/0607 ,  H03M1/08 ,  H03M1/109 ,  H03M1/121 ,  H03M1/1215

Abstract: The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count. The error estimation unit of the time-interleaved ADC system includes a counting unit, a subtractor and an integrator. The method for estimating an offset error in a time-interleaved ADC includes determining signs of the signals and outputting corresponding values by the counting unit. The values are further compared and integrated to estimate the offset error. The method for estimating a gain error in a time-interleaved ADC includes determining the absolute values of the signals and comparing the absolute values with a predetermined threshold value. The comparison results are further integrated to estimate the gain error.

Abstract translation: 本公开涉及时间交织的模数转换器（ADC）中的背景估计领域。 更具体地，本公开涉及用于基于样本计数的时间交织ADC中的偏移和增益误差的背景估计的系统和方法。 时间交织的ADC系统的误差估计单元包括计数单元，减法器和积分器。 用于估计时间交替ADC中的偏移误差的方法包括确定信号的符号并由计数单元输出相应的值。 进一步比较和积分这些值以估计偏移误差。 用于估计时间交替ADC中的增益误差的方法包括确定信号的绝对值并将绝对值与预定阈值进行比较。 比较结果被进一步整合以估计增益误差。

公开(公告)号：US09124286B1

公开(公告)日：2015-09-01

申请号：US14183159

申请日：2014-02-18

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： Stéphane Bouvier ,  Sylvain Dumont ,  Luis Rolindez

IPC: H03M1/10 ,  H03M1/12 ,  H03M1/36 ,  H03M1/46

CPC classification number: H03M1/181 ,  H03M1/167 ,  H03M1/365

Abstract: Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the other circuit receives the reset signal, the ADC may enter a protection mode to protect the ADC by ensuring that the excessive input signal is not propagated to subsequent stages.

Abstract translation: 提供了用于保护模数转换器（ADC）的系统和方法。 所提供的系统和方法利用ADC级的电路中的比较器将参考信号与输入信号进行比较，并在输入信号超过参考信号时输出一个或多个最大信号。 当接收到预定数量的最大信号时，ADC阶段的解码器可以在ADC的阶段将复位信号输出到另一个电路。 当另一个电路接收到复位信号时，ADC可能进入保护模式以保护ADC，以确保过多的输入信号不会传播到后续级。

公开(公告)号：US20150156284A1

公开(公告)日：2015-06-04

申请号：US14134998

申请日：2013-12-19

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： Mohammad Shahanshah Akhter ,  Bachir Berkane

IPC: H04L29/06

CPC classification number: H04L69/08 ,  H04L29/06 ,  H04L69/04 ,  H04L69/22 ,  H04W88/085

Abstract: A method and apparatus provides a parameter estimation processor configured to estimate parameters used to compress data for transmission over a serial data link. The parameter estimation processor includes a processor. The processor includes user programmable inputs. The user programmable inputs set an input data packet length, a target compression ratio, and a resampling factor and allow filter parameters to be set. Input data information is received from an input data buffer of a data sample compressor. The processor performs a function that: (a) adjusting a target compression ratio by a first compression ratio to determine a remaining compression ratio when the resampling operation is enabled; (b) estimating a set of compression parameters that are used to achieve the remaining compression ratio, the set of compression parameters includes an attenuation value, filter order, a type of encoding; and (c) sends the set of compression parameters to the data sample compressor. The data sample compressor applies the compression parameters to a packet of input data and outputs a plurality of compressed data words.

Abstract translation: 一种方法和装置提供一种参数估计处理器，其被配置为估计用于压缩数据以用于通过串行数据链路传输的参数。 参数估计处理器包括处理器。 处理器包括用户可编程输入。 用户可编程输入设置输入数据分组长度，目标压缩比和重采样因子，并允许设置滤波器参数。 从数据样本压缩器的输入数据缓冲器接收输入数据信息。 处理器执行以下功能：（a）当启用重采样操作时，调整目标压缩比第一压缩比以确定剩余压缩比; （b）估计用于实现剩余压缩比的一组压缩参数，所述压缩参数集合包括衰减值，滤波器次序，编码类型; 和（c）将该组压缩参数发送到数据样本压缩器。 数据采样压缩器将压缩参数应用于输入数据的分组并输出多个压缩数据字。

公开(公告)号：US20140266015A1

公开(公告)日：2014-09-18

申请号：US14212947

申请日：2014-03-14

Applicant: Integrated Device Technology, Inc.

Inventor： Trevor Newlin

IPC: H02J7/00

CPC classification number: H02J7/0091

Abstract: A charging system includes a temperature sensor to generate a temperature signal responsive to a temperature of an energy storage device. A circuit temperature sensor generates a circuit temperature signal responsive to a temperature of a semiconductor device. A charge adjuster generates a desired current signal responsive to the temperature signal and the circuit temperature signal. A comparator compares a charge-current level signal to the desired current signal to generate a charge adjustment signal. A charge controller on the semiconductor device generates and adjusts a current of a charging signal for charging the energy storage device responsive to the charge adjustment signal. The charge adjuster may generate a reduction signal when the temperature signal is above a throttle threshold, reduce a digital desired current signal responsive to the reduction signal, and convert the digital desired current signal to the desired current signal as an analog signal.

Abstract translation: 充电系统包括温度传感器，用于响应于能量存储装置的温度产生温度信号。 电路温度传感器响应于半导体器件的温度产生电路温度信号。 电荷调节器响应于温度信号和电路温度信号产生期望的电流信号。 比较器将充电电流电平信号与期望的电流信号进行比较，以产生电荷调节信号。 半导体装置上的充电控制器响应于电荷调节信号产生并调节用于对能量存储装置充电的充电信号的电流。 当温度信号高于节流门限时，电荷调节器可以产生减小信号，响应于减小信号减小数字期望电流信号，并将数字期望电流信号转换为期望的电流信号作为模拟信号。