公开(公告)号：US20170302299A1

公开(公告)日：2017-10-19

申请号：US15188995

申请日：2016-06-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Cheng-Che Yang ,  Shao-Wei Yen ,  Kuo-Hsin Lai

IPC: H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1068 ,  G11C29/52 ,  G11C29/702 ,  H03M13/1102 ,  H03M13/2927 ,  H03M13/3776

Abstract: A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.

公开(公告)号：US09773565B1

公开(公告)日：2017-09-26

申请号：US15458037

申请日：2017-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G11C16/06 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G11C16/32

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/32 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52

Abstract: A memory retry-read method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a sequence of several retry-read parameter groups according to several weights of the retry-read parameter groups; reading data from a physical programming unit according to a read voltage; if the data are unable to be corrected by a corresponding ECC code, choosing an adjustment retry-read parameter group from the retry-read parameter groups; retrying reading new data from the physical programming unit according to the adjustment retry-read parameter group; if the new data are able to be corrected by the corresponding ECC code, determining the adjustment retry-read parameter group to be an available retry-read parameter group; and adjusting the weight of the available retry-read parameter group.

公开(公告)号：US09760509B2

公开(公告)日：2017-09-12

申请号：US14480643

申请日：2014-09-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiang-Hsiung Yu ,  Yuan-Cheng Chang ,  Wei-Cheng Wu

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F13/1673

Abstract: A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information.

公开(公告)号：US20170255389A1

公开(公告)日：2017-09-07

申请号：US15140494

申请日：2016-04-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

CPC classification number: G06F3/0605 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F12/0246

Abstract: A data transmitting method for a memory storage device is provided. The method includes: detecting a temperature of the memory storage device; and determining whether the temperature of the memory storage device is greater than a temperature threshold. If the temperature is greater than the temperature threshold, first data is written into a rewritable non-volatile memory module within a first delay time according to a delay count corresponding to a unit temperature.

公开(公告)号：US20170242748A1

公开(公告)日：2017-08-24

申请号：US15096284

申请日：2016-04-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin

IPC: G06F11/10 ,  H03M13/45 ,  H03M13/11 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/458 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: programming a first memory cell in a rewritable non-volatile memory module; reading the first memory cell based on a first hard-decision voltage level to obtain first hard-bit information and perform a hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a first type memory cell, reading the first memory cell based on a second hard-decision voltage level to obtain second hard-bit information and perform another hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a second type memory cell, reading the first memory cell based on multiple second soft-decision voltage level to obtain soft-bit information and perform soft-decoding process accordingly. Therefore, a balance can be maintained between a decoding speed and a decoding success rate.

公开(公告)号：US09721669B2

公开(公告)日：2017-08-01

申请号：US14887332

申请日：2015-10-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Hua Chu

IPC: G06F12/00 ,  G11C16/22 ,  G11C16/32 ,  G11C16/34 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06

CPC classification number: G11C16/22 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0646 ,  G11C16/225 ,  G11C16/32 ,  G11C16/3418

Abstract: A data protection method for a memory storage apparatus is provided. The method includes obtaining a current system time from a host system as a boot time, if the memory storage apparatus is powered on, and a basic input/output system of the host system loads and executes instruction programs in the expansion ROM of the memory storage apparatus for transmitting the current system time to the memory storage apparatus. The method also includes obtaining a shutdown time corresponding to the memory storage apparatus; calculating an off time from the shutdown time to the boot time and performing a refresh operation on physical erasing units of a rewritable non-volatile memory in the memory storage apparatus if the off time is longer than an off time threshold.

公开(公告)号：US09716506B2

公开(公告)日：2017-07-25

申请号：US15261877

申请日：2016-09-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Yung Chen ,  Yu-Chiang Liao

IPC: H03L7/091 ,  G11C7/22 ,  H03L7/087 ,  H03L7/08 ,  H03L7/099 ,  H03L7/107 ,  H03L7/22 ,  G11C7/10

CPC classification number: H03L7/091 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0802 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/033

Abstract: A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.

公开(公告)号：US09703698B2

公开(公告)日：2017-07-11

申请号：US13935572

申请日：2013-07-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Kim-Hon Wong ,  Hao-Zhi Lee ,  Hung-Chun Lin ,  Chun-Yen Chang

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/56 ,  G11C29/00 ,  G11C7/04

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C7/04 ,  G11C11/5628 ,  G11C29/82

Abstract: A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.

公开(公告)号：US20170177260A1

公开(公告)日：2017-06-22

申请号：US15052891

申请日：2016-02-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Hua Chu

IPC: G06F3/06 ,  G11C16/14

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0688

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: configuring a plurality of first type super physical units, and each of the first type super physical units includes at least two good physical erasing units which may be programmed simultaneously. The method also includes: configuring at least one second type super physical unit, and the at least one second type super physical unit includes at least two good physical erasing units which may not be programmed simultaneously.

公开(公告)号：US09685221B1

公开(公告)日：2017-06-20

申请号：US15241094

申请日：2016-08-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G11C16/30 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4074 ,  G06F13/16 ,  G06F13/1668 ,  G11C5/147 ,  G11C11/4093 ,  G11C16/30

Abstract: A memory control circuit unit, a memory storage device and a reference voltage generation method are provided. The method comprises: detecting a first impedance characteristic of a memory controller via a first connection interface of a memory interface and detecting a second impedance characteristic of a volatile memory via a second connection interface of the memory interface; generating an internal reference voltage according to a detection result; and resolving data signal received by the memory interface according to the internal reference voltage. Therefore, an influence on the internal reference voltage owing to the manufacture deviation of impedance element of the memory controller and/or the volatile memory can be reduced.