公开(公告)号：US20160276238A1

公开(公告)日：2016-09-22

申请号：US15167662

申请日：2016-05-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯周围形成密封剂。 在半导体管芯和密封剂的第一表面上形成积聚互连结构。 第一支撑层形成在半导体管芯的第二表面上，作为与积聚互连结构相对设置的支撑衬底或硅晶片。 第二支撑层形成在第一支撑层之上，并且包括纤维增强聚合物复合材料，其包括占地面积，其包括大于或等于半导体管芯的覆盖区域的面积。 半导体管芯的厚度小于450微米（μm）。 半导体管芯的厚度比半导体器件的总厚度和积层互连结构和第二支撑层的厚度之差小至少1μm。

公开(公告)号：US20160276232A1

公开(公告)日：2016-09-22

申请号：US15169535

申请日：2016-05-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract translation: 半导体器件具有形成在载体上的第一互连结构。 在测试第一互连结构之后，将半导体管芯设置在第一互连结构上以使其已知良好。 半导体芯片在一个已知的好的芯片中。 在第一互连结构上形成垂直互连结构，例如凸块或凸块凸块。 分立半导体器件设置在第一互连结构或第二互连结构上。 密封剂沉积在半导体管芯，第一互连结构和垂直互连结构之上。 去除一部分密封剂以露出垂直互连结构。 第二互连结构形成在密封剂上并电连接到垂直互连结构。 第一互连结构或第二互连结构包括具有嵌入的玻璃布，玻璃交叉，填充物或纤维的绝缘层。

公开(公告)号：US12288753B2

公开(公告)日：2025-04-29

申请号：US17369654

申请日：2021-07-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  KyoWang Koo ,  SungWon Cho

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/04 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device has a substrate. A lid is disposed over the substrate. An encapsulant is deposited over the substrate. A film mask is disposed over the encapsulant with the lid exposed from the film mask and encapsulant. A conductive layer is formed over the film mask, encapsulant, and lid. The film mask is removed after forming the conductive layer.

公开(公告)号：US20250087499A1

公开(公告)日：2025-03-13

申请号：US18463613

申请日：2023-09-08

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Kirak Son ,  JungHwan Jang ,  KyungHan Ryu ,  MyongSuk Kang ,  JaeSeong Choi ,  YoungJoon Yoon

IPC: H01L21/48 ,  H01L23/498

Abstract: A semiconductor device has a carrier. A first redistribution layer is formed over the carrier. A capping layer is formed on the first redistribution layer. The capping layer includes an anti-reflective coating. An insulating layer is formed on the capping layer. An opening is formed through the insulating layer using photolithography. A conductive layer is formed in the opening.

公开(公告)号：US20250054902A1

公开(公告)日：2025-02-13

申请号：US18448913

申请日：2023-08-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Peik Eng Ooi

IPC: H01L23/00 ,  H01L23/495

Abstract: A semiconductor device has an electrical component with bump structures. A conductive layer is formed over the electrical component with a first segment of the conductive layer coupled between the first and second bumps. The electrical component is disposed on a paddle of a lead frame interposer. A first bond wire is coupled between a first lead and the first bump. A second bond wire is coupled between a second lead and the second bump. A third bond wire is coupled between a third lead and a third bump, and a fourth bond wire is coupled between a fourth lead and a fourth bump. A fifth bond wire coupled between the second lead and third lead and a second segment of the conductive layer is coupled between the third bump and fourth bump to constitute a daisy chain loop to test continuity of the bump structures.

公开(公告)号：US12211803B2

公开(公告)日：2025-01-28

申请号：US18390051

申请日：2023-12-20

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  Gwang Kim ,  Junho Ye ,  YouJoung Choi ,  MinKyung Kim ,  Yongwoo Lee ,  Namgu Kim

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01Q1/24 ,  H01Q1/40

Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.

公开(公告)号：US20250006608A1

公开(公告)日：2025-01-02

申请号：US18344920

申请日：2023-06-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Linda Pei Ee Chua ,  Kai Chong Chan ,  Rowena Zarate ,  Marites Roque ,  Yi Jing Eric Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.

公开(公告)号：US20240421172A1

公开(公告)日：2024-12-19

申请号：US18746062

申请日：2024-06-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： BumRyul MAENG ,  MyungHo JUNG

IPC: H01L27/146

Abstract: An optical sensor package comprises: a base substrate having a window; a first optical sensor mounted on a front surface of the base substrate, with its light receiving surface facing towards and aligned with the window; a first light-pervious encapsulant mold covering the light receiving surface of the first optical sensor; a first encapsulant layer formed on the front surface of the base substrate, wherein the first encapsulant layer comprises interlayer connects passing therethrough; an interposer mounted on the first encapsulant layer and electrically coupled to the base substrate through the interlayer connects of the first encapsulant layer; a second optical sensor mounted on a front surface of the interposer, with its light receiving surface facing away from the interposer; a second light-pervious encapsulant mold covering the light receiving surface of the second optical sensor; and a second encapsulant layer formed on the front surface of the interposer.

公开(公告)号：US20240421138A1

公开(公告)日：2024-12-19

申请号：US18739404

申请日：2024-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JiSeon LEE ,  BumRyul MAENG ,  HyunKyu LEE

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/538 ,  H01L25/00

Abstract: A semiconductor package and a method for making the same are provided. The semiconductor package includes: a substrate having a lower substrate surface and an upper substrate surface; a first interposer attached on the upper substrate surface; at least one first electronic component mounted on and electronically connected with the first interposer; a second interposer disposed above the at least one first electronic component, wherein the second interposer has a concave portion and a protruding portion, the at least one first electronic component is accommodated in the concave portion, and the protruding portion is mounted on the upper substrate surface; and at least one second electronic component mounted on and electronically connected with the second interposer.

公开(公告)号：US20240379511A1

公开(公告)日：2024-11-14

申请号：US18314626

申请日：2023-05-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Chunhe Quan ,  JinYoung Lee ,  Hyungwoo Park

IPC: H01L23/498 ,  H01L21/48 ,  H01Q1/22

Abstract: A semiconductor device has a substrate and a first electrical interconnect structure formed over a first surface of the substrate. A second electrical interconnect structure is formed over a second surface of the substrate. An electrical component is disposed over the first surface of the substrate or over the second surface of the substrate. A first antenna is formed over the first electrical interconnect structure. A second antenna is formed over the second electrical interconnect structure. The first electrical interconnect structure has an insulating material formed over the first surface of the substrate, and a conductive via formed through the insulating material. Alternatively, the first electrical interconnect structure has an insulating layer formed over the first surface of the substrate, a conductive layer formed over the insulating layer, and a conductive via formed through the insulating layer and conductive layer.