公开(公告)号：US08916474B2

公开(公告)日：2014-12-23

申请号：US13769769

申请日：2013-02-18

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef H•glauer

IPC: H01L21/311 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/03011 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05584 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/16145 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29366 ,  H01L2224/29369 ,  H01L2224/29371 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2224/83805 ,  H01L2224/83862 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01023 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.

Abstract translation: 根据本发明的实施例，半导体模块包括具有设置在第一密封剂中的第一半导体管芯的第一半导体封装。 开口设置在第一密封剂中。 包括第二半导体管芯的第二半导体封装设置在第二密封剂中。 第二半导体封装至少部分地设置在第一密封剂的开口内。

公开(公告)号：US20140197523A1

公开(公告)日：2014-07-17

申请号：US13742426

申请日：2013-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Marco Seibt

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/495 ,  H01L21/56 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3731 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/291 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed over a side of the carrier.

Abstract translation: 提供了芯片布置，芯片布置包括：载体; 至少一个芯片，包括设置在所述载体上的至少一个接触焊盘; 至少部分地围绕所述至少一个芯片和所述载体的封装材料; 以及设置在载体的一侧上的至少一个低温共烧陶瓷片。

公开(公告)号：US20140151866A1

公开(公告)日：2014-06-05

申请号：US13691587

申请日：2012-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L23/293 ,  H01L23/495 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/562 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/85099 ,  H01L2224/85399 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: An assembled semiconductor device and a method of making an assembled semiconductor device are disclosed. In one embodiment the assembled device includes a carrier having a first thickness, a connection layer disposed on the carrier and a chip disposed on the connection layer, the chip having a second thickness, wherein the second thickness is larger than the first thickness.

Abstract translation: 公开了一种组装的半导体器件和制造组装的半导体器件的方法。 在一个实施例中，组装的装置包括具有第一厚度的载体，设置在载体上的连接层和设置在连接层上的芯片，该芯片具有第二厚度，其中第二厚度大于第一厚度。

公开(公告)号：US20140151856A1

公开(公告)日：2014-06-05

申请号：US13693205

申请日：2012-12-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/34 ,  H01L21/56

CPC classification number: H01L23/34 ,  H01L21/56 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈r and the thermal conductivity λ of the insulation layer satisfy the condition λ·∈r

Abstract translation: 芯片模块包括载体，布置在载体上或嵌入载体内部的半导体芯片，以及至少部分覆盖载体的表面的绝缘层。 绝缘层的介电常数εr和热导率λ满足条件λ·∈r<4.0 W·m-1·K-1。

公开(公告)号：US20130328213A1

公开(公告)日：2013-12-12

申请号：US13965630

申请日：2013-08-13

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Henrik Ewe ,  Klaus Schiess ,  Manfred Mengel

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

Abstract: One aspect is a device including a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer. A semiconductor chip is attached to the carrier and a second insulating layer is over the carrier and the semiconductor chip. A metal layer is over the second insulating layer. A second through-connection is through the second insulating layer electrically coupling the semiconductor chip to the metal layer. A third through-connection is through the second insulating layer electrically coupling the carrier to the metal layer.

Abstract translation: 一个方面是包括载体的器件，其包括第一导电层，在第一导电层上的第一绝缘层，以及从第一绝缘层的第一面到第一绝缘层的第二面的至少一个第一通孔连接 。 半导体芯片附着到载体上，第二绝缘层位于载体和半导体芯片之上。 金属层在第二绝缘层之上。 第二直通连接通过第二绝缘层将半导体芯片电耦合到金属层。 第三直通连接是通过第二绝缘层将载体电耦合到金属层。

公开(公告)号：US12068226B2

公开(公告)日：2024-08-20

申请号：US17473423

申请日：2021-09-13

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L23/473 ,  H01L25/07

CPC classification number: H01L23/473 ,  H01L25/072

Abstract: A semiconductor device assembly includes a cooling system, a plurality of semiconductor packages, each including a semiconductor die and an encapsulant body, and a multi-device thermal interface interposed between the plurality of semiconductor packages and the cooling system, wherein the semiconductor packages are each configured as surface mount devices, and wherein the multi-device thermal interface thermally couples each of the semiconductor packages to the cooling system.

公开(公告)号：US11929298B2

公开(公告)日：2024-03-12

申请号：US17097098

申请日：2020-11-13

Applicant: Infineon Technologies AG

Inventor： Jo Ean Joanna Chye ,  Edward Fuergut ,  Ralf Otremba

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L23/46 ,  H01L23/495

CPC classification number: H01L23/367 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/46 ,  H01L23/49568

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

公开(公告)号：US20210035945A1

公开(公告)日：2021-02-04

申请号：US16943084

申请日：2020-07-30

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Ralf Otremba ,  Stefan Schwab

IPC: H01L23/00

Abstract: An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component.

公开(公告)号：US20210035876A1

公开(公告)日：2021-02-04

申请号：US16939303

申请日：2020-07-27

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Markus Dinkel ,  Josef Hoeglauer ,  Angela Kessler

IPC: H01L23/31 ,  H01L23/495 ,  H01L25/065

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body and a semiconductor component encapsulated in the package body. A cavity is formed in a bottom surface of the package body.

公开(公告)号：US20210020539A1

公开(公告)日：2021-01-21

申请号：US16929223

申请日：2020-07-15

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Teck Sim Lee ,  Klaus Schiess ,  Xaver Schloegel ,  Lee Shuang Wang ,  Mohd Hasrul Zulkifli

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/31 ,  H01L23/12

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.