公开(公告)号：US20230420574A1

公开(公告)日：2023-12-28

申请号：US17847555

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Rambert Nahm ,  Natalie Briggs ,  Susmita Ghose ,  Glenn Glass ,  Devin R. Merrill ,  Aaron A. Budrevich ,  Shruti Subramanian ,  Biswajeet Guha ,  William Hsu ,  Adedapo A. Oni ,  Rahul Ramamurthy ,  Anupama Bowonder ,  Hsin-Ying Tseng ,  Rajat K. Paul ,  Marko Radosavljevic

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：US20230420562A1

公开(公告)日：2023-12-28

申请号：US17809329

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Munzarin F. Qayyum ,  Nicole K. Thomas ,  Rohit Galatage ,  Patrick Morrow ,  Jami A. Wiedemer ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66795

Abstract: Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.

公开(公告)号：US11848362B2

公开(公告)日：2023-12-19

申请号：US16388479

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann Christian Rode ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/417 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.

公开(公告)号：US20230395718A1

公开(公告)日：2023-12-07

申请号：US17833050

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Nitesh Kumar ,  Jami A. Wiedemer ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Patrick Morrow ,  Rohit Galatage ,  David N. Goldstein ,  Christopher J. Jezewski

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/7845 ,  H01L29/42392 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/45

Abstract: An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.

公开(公告)号：US11791221B2

公开(公告)日：2023-10-17

申请号：US16283673

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul B. Fischer

IPC: H01L21/8258 ,  H01L29/205 ,  H01L29/40 ,  H01L27/092 ,  H01L29/16 ,  H01L25/065 ,  H01L29/66 ,  H01L29/08 ,  H01L27/12 ,  H01L29/778 ,  H01L29/20 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/8258 ,  H01L25/0652 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor layer transfer. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by, first, depositing a semiconductor material layer, a portion of which will later serve as a channel material of the non-III-N transistor, on a support structure different from that on which the III-N semiconductor material for the III-N transistor is provided, and then performing layer transfer of said semiconductor material layer to the support structure with the III-N material, e.g., by oxide-to-oxide bonding, advantageously enabling implementation of both types of transistors on a single support structure. Such integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US11777022B2

公开(公告)日：2023-10-03

申请号：US16650307

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/402 ,  H01L29/66462

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for transistors including first and second semiconductor materials between source and drain regions. An example apparatus includes a first semiconductor material and a second semiconductor material adjacent the first semiconductor material. The example apparatus further includes a source proximate the first semiconductor material and spaced apart from the second semiconductor material. The example apparatus also includes a drain proximate the second semiconductor material and spaced apart from the first semiconductor material. The example apparatus includes a gate located between the source and the drain.

公开(公告)号：US11757027B2

公开(公告)日：2023-09-12

申请号：US16218882

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann C. Rode ,  Paul Fischer ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/778 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/0883 ,  H01L29/66462 ,  H01L29/66545 ,  H01L29/78

Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.

公开(公告)号：US11670709B2

公开(公告)日：2023-06-06

申请号：US16297837

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Paul B. Fischer ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42356 ,  H01L29/66462

Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.

公开(公告)号：US11670637B2

公开(公告)日：2023-06-06

申请号：US16279102

申请日：2019-02-19

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/20 ,  H01L27/06 ,  H01L29/15 ,  H01L29/778 ,  H01L21/8252 ,  H01L23/66 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/8252 ,  H01L23/535 ,  H01L23/66 ,  H01L27/0605 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.

公开(公告)号：US20230132749A1

公开(公告)日：2023-05-04

申请号：US17517065

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Marko Radosavljevic ,  Cheng-Ying Huang ,  Willy Rachmady ,  Gilbert Dewey ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092

Abstract: Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. In an example, an upper (e.g., n-channel) device and a lower (e.g., p-channel) device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where the upper device is located vertically above the lower device. According to some embodiments, an internal spacer structure extends between the nanoribbons of the upper device and the nanoribbons of the lower device along the vertical direction, where the spacer structure has a stepwise or an otherwise outwardly protruding profile as it extends between the nanoribbons of the upper device and the lower device. Accordingly, in one example, a gate structure formed around the nanoribbons of both the n-channel device and the p-channel device exhibits a greater width in the region between the nanoribbons of the n-channel device and the nanoribbons of the p-channel device.