公开(公告)号：US20230138575A1

公开(公告)日：2023-05-04

申请号：US17539677

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun ZHANG ,  Lei LIU ,  Yuancheng YANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L21/02 ,  H01L21/67

Abstract: Methods for thermal treatment on a semiconductor device is disclosed. One method includes obtaining a pattern of a treatment area having amorphous silicon, aligning a laser beam with the treatment area, the laser beam in a focused laser spot having a spot area equal to or greater than the treatment area, and performing a laser anneal on the treatment area by emitting the laser beam towards the treatment area for a treatment period.

公开(公告)号：US20220246527A1

公开(公告)日：2022-08-04

申请号：US17725059

申请日：2022-04-20

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

公开(公告)号：US20220139837A1

公开(公告)日：2022-05-05

申请号：US17575158

申请日：2022-01-13

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Lei LIU ,  Zhiliang XIA

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11524 ,  H01L21/321 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

公开(公告)号：US20210384309A1

公开(公告)日：2021-12-09

申请号：US17445434

申请日：2021-08-19

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L29/423 ,  H01L27/11529 ,  H01L21/28 ,  H01L27/11573

Abstract: Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

公开(公告)号：US20210367051A1

公开(公告)日：2021-11-25

申请号：US16918259

申请日：2020-07-01

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L29/423 ,  H01L27/11529 ,  H01L27/11573 ,  H01L21/28

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

公开(公告)号：US20210358945A1

公开(公告)日：2021-11-18

申请号：US17113492

申请日：2020-12-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong ZHANG ,  Zhongwang SUN ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524

Abstract: In a method for fabricating a semiconductor device, an initial stack is formed. The initial stack is formed of sacrificial layers and insulating layers that are alternatingly disposed over a substrate, and includes a first connection region, a first array region, and a second connection region that are disposed sequentially. A first initial staircase is formed in the first connection region and formed in a first group of sacrificial layers and insulating layers. A first top select gate staircase is formed in the second connection region, and formed in a second group of sacrificial layers and insulating layers. An etching process is subsequently performed in the first connection region to shift the first initial staircase toward the substrate along a vertical direction perpendicular to the substrate so as to form a first bottom select gate staircase.

公开(公告)号：US20210296325A1

公开(公告)日：2021-09-23

申请号：US16895410

申请日：2020-06-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Linchun WU ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11565

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a sacrificial layer over the cover layer, depositing a layer stack over the sacrificial layer, forming a channel layer extending through the layer stack and the sacrificial layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate, removing the cover layer, and performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate. The layer stack includes first stack layers and second stack layers that are alternately stacked.

公开(公告)号：US20210272632A1

公开(公告)日：2021-09-02

申请号：US17317215

申请日：2021-05-11

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zongliang HUO ,  Li Hong XIAO ,  Zhiliang XIA

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefor are disclosed. In an example, the memory device includes a substrate and one or more peripheral devices on the substrate. The memory device also includes one or more interconnect layers and a semiconductor layer disposed over the one or more interconnect layers. A layer stack having alternating conductor and insulator layers is disposed above the semiconductor layer. A plurality of structures extend vertically through the layer stack. A first set of conductive lines are electrically coupled with a first set of the plurality of structures and a second set of conductive lines are electrically coupled with a second set of the plurality of structures different from the first set. The first and second sets of conductive lines are vertically distanced from opposite ends of the plurality of structures.

公开(公告)号：US20210225872A1

公开(公告)日：2021-07-22

申请号：US17113484

申请日：2020-12-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhongwang SUN ,  Rui SU ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C8/14

Abstract: A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers that are stacked alternatingly over a substrate. The semiconductor device also includes a first dielectric trench structure. The first dielectric trench structure is positioned in a bottom select gate (BSG) layer of the word line layers to separate the BSG layer and extends in a first direction of substrate. The semiconductor device further includes a second dielectric trench structure. The second dielectric trench structure is positioned in a top select gate (TSG) layer of the word line layers to separate the TSG layer and extends in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate that is perpendicular to the first direction.

公开(公告)号：US20200335514A1

公开(公告)日：2020-10-22

申请号：US16918683

申请日：2020-07-01

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Zhiliang XIA ,  Ping YAN ,  Guangji LI ,  Zongliang HUO

IPC: H01L27/11578 ,  H01L27/11575 ,  H01L21/762 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.