公开(公告)号：US09510445B2

公开(公告)日：2016-11-29

申请号：US14360836

申请日：2012-11-26

Applicant: SNU R&DB FOUNDATION ,  KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Young Chang Joo ,  In Suk Choi ,  Myoung Woon Moon ,  Byoung Joon Kim ,  Min Suk Jung

IPC: B05D5/00 ,  H05K1/09 ,  H05K3/14

CPC classification number: H05K1/09 ,  H05K3/146 ,  H05K2201/0154 ,  H05K2201/0969

Abstract: In the present invention, a copper electrode having a nanohole structure is prepared by using a polymer substrate in the form of nanopillars in order to avoid fatigue fracture that causes degradation of electrical and mechanical properties of a flexible electrode during repetitive bending of a typical metal electrode. The nanohole structure may annihilate dislocations to suppress the initiation of fracture and may blunt crack tips to delay the propagation of damage. Therefore, the nanohole electrode exhibits very small changes in electrical resistance during a bending fatigue test.

Abstract translation: 在本发明中，通过使用纳米柱形式的聚合物基材来制备具有纳米孔结构的铜电极，以避免在典型金属电极的重复弯曲过程中导致柔性电极的电气和机械性能降低的疲劳断裂 。 纳米孔结构可以消除位错以抑制断裂的开始，并且可能钝化裂纹尖端以延迟损伤的传播。 因此，在弯曲疲劳试验中，纳米孔电极的电阻变化很小。

公开(公告)号：US20160323992A1

公开(公告)日：2016-11-03

申请号：US15138116

申请日：2016-04-25

Applicant: FINISAR CORPORATION

Inventor： Henry Meyer Daghighian ,  Steven C. Bird

IPC: H05K1/02 ,  H05K1/11 ,  G02B6/12 ,  H05K1/09 ,  G02B6/122 ,  G02B6/136 ,  H05K1/03 ,  H01P3/08

CPC classification number: H05K1/0274 ,  G02B6/12007 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B6/4269 ,  G02B2006/12035 ,  G02B2006/121 ,  G02B2006/12104 ,  G02B2006/12107 ,  G02B2006/12164 ,  H01P3/081 ,  H05K1/0201 ,  H05K1/0207 ,  H05K1/0209 ,  H05K1/024 ,  H05K1/028 ,  H05K1/032 ,  H05K1/09 ,  H05K1/115 ,  H05K3/323 ,  H05K3/4605 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4638 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/09918

Abstract: A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.

Abstract translation: 印刷电路板可以包括包含AIN薄膜和作为AIN薄膜的载体衬底的高频聚合物层的氮化铝（AlN）衬底。 AIN衬底形成印刷电路板的第一层。 AIN衬底包括散热器，其横向散布来自印刷电路板上的散热器的热量，以形成与印刷电路板上的信号路径平行的散热路径。 印刷电路板可以包括与AIN衬底对准并与其结合的主衬底。 主衬底可以包括印刷电路板的一个或多个附加层。

公开(公告)号：US20160316568A1

公开(公告)日：2016-10-27

申请号：US15200003

申请日：2016-07-01

Applicant: AZOTEK CO., LTD.

Inventor： Hung-Jung LEE

IPC: H05K3/00 ,  H05K1/05 ,  H05K1/03

CPC classification number: H05K3/007 ,  H05K1/028 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/0346 ,  H05K1/0393 ,  H05K1/056 ,  H05K3/0011 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/44 ,  H05K3/46 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2203/06 ,  H05K2203/10 ,  H05K2203/1536 ,  Y10T156/10 ,  Y10T428/1438 ,  Y10T428/24355

Abstract: A metal substrate includes a first insulating substrate, a second insulating substrate, a first metal layer, a second metal layer and a release layer. The first insulating substrate has a first modified surface and a second surface opposite to the first modified surface. The first metal layer faces the second surface. The release layer is bonded on the first modified surface. The second insulating substrate is bonded on a side of the release layer, such that the release layer is between the first modified surface and the second insulating substrate. The second metal layer is disposed on a side of the second insulating substrate, such that the second insulating substrate is between the release layer and the second metal layer. An original surface roughness of the first modified surface has a variation substantially less than 10% after the first modified surface is released from the release layer.

公开(公告)号：US20160315044A1

公开(公告)日：2016-10-27

申请号：US15199913

申请日：2016-06-30

Applicant: Industrial Technology Research Institute

Inventor： Wei-Yuan Cheng ,  Chen-Chu Tsai ,  Yuh-Zheng Lee

IPC: H01L23/498 ,  H01L21/683 ,  H01L23/31

CPC classification number: H05K1/028 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16 ,  H01L2924/181 ,  H05K1/0281 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/007 ,  H05K3/4038 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/10106 ,  H05K2201/10128 ,  H05K2201/2009 ,  H05K2203/1178 ,  H01L2924/00012

Abstract: According to embodiments of the disclosure, an electronic device package may include a wire layer and a rigid element. The wire layer includes a first surface and a second surface opposite to each other, and the second surface of the wire layer has at least one coarse structure. A portion of the second surface having the coarse structure has a greater roughness than another portion of the second surface. The rigid element is disposed on the first surface of the wire layer, wherein a stiffness of the rigid element is greater than a stiffness of the wire layer and a projection area of the coarse structure on the first surface of the wire layer overlaps an edge of the rigid element.

Abstract translation: 根据本公开的实施例，电子设备封装可以包括导线层和刚性元件。 线层包括彼此相对的第一表面和第二表面，并且线层的第二表面具有至少一个粗糙结构。 具有粗糙结构的第二表面的一部分具有比第二表面的另一部分更大的粗糙度。 刚性元件设置在线层的第一表面上，其中刚性元件的刚度大于金属丝层的刚度，并且粗糙结构在金属丝层的第一表面上的投影区域与 刚性元素。

公开(公告)号：US20160309594A1

公开(公告)日：2016-10-20

申请号：US15194995

申请日：2016-06-28

Applicant: MC10, Inc.

Inventor： Yung-Yu Hsu

IPC: H05K1/18 ,  H05K1/09 ,  H05K1/03 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/185 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0283 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/118 ,  H05K1/147 ,  H05K1/148 ,  H05K1/189 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/09245 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2201/2009

Abstract: Buffer structures are provided that can be used to reduce a strain in a conformable electronic system that includes compliant components in electrical communication with more rigid device components. The buffer structures are disposed on, or at least partially embedded in, the conformable electronic system such that the buffer structures overlap with at least a portion of a junction region between a compliant component and a more rigid device component. The buffer structure can have a higher value of Young's modulus than an encapsulant of the conformable electronic system.

Abstract translation: 提供缓冲结构，其可以用于减少适应电子系统中的应变，其包括与更刚性的装置部件电连通的顺应部件。 缓冲结构设置在适配电子系统上或至少部分嵌入适配电子系统中，使得缓冲结构与柔顺部件和更刚性的器件部件之间的连接区域的至少一部分重叠。 缓冲结构可以具有比适形电子系统的密封剂更高的杨氏模量值。

公开(公告)号：US20160300787A1

公开(公告)日：2016-10-13

申请号：US14830955

申请日：2015-08-20

Applicant: SK hynix Inc.

Inventor： Ki Jun SUNG

IPC: H01L23/498 ,  H05K1/03 ,  H05K1/09 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/0326 ,  H05K1/0346 ,  H05K1/09 ,  H05K3/3436 ,  H05K3/4015 ,  H05K3/4673 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/10242 ,  H05K2203/1316

Abstract: A substrate may include a body having a first surface and a second surface opposite to each other, at least one first wiring pattern disposed on the first surface of the body to include a bonding finger, an upper insulating pattern disposed on the first surface of the body to cover the overall surface of the at least one first wiring pattern except the bonding finger, and a second wiring pattern disposed on the second surface of the body. The substrate may include a lower insulating pattern disposed on the second surface of the body to cover the second wiring pattern, and a first via electrode penetrating the body from the first surface to the second surface and coupling the at least one first wiring pattern to the second wiring pattern. The body may include a first film and the upper and lower insulating patterns may include second films.

Abstract translation: 衬底可以包括具有彼此相对的第一表面和第二表面的主体，设置在主体的第一表面上的至少一个第一布线图案，以包括接合指状物，上绝缘图案设置在第一表面上 主体覆盖除了接合手指之外的至少一个第一布线图案的整个表面，以及布置在主体的第二表面上的第二布线图案。 衬底可以包括布置在主体的第二表面上以覆盖第二布线图案的下绝缘图案，以及从第一表面穿过主体到第二表面的第一通孔电极，并将至少一个第一布线图案耦合到 第二布线图。 主体可以包括第一膜，并且上和下绝缘图案可以包括第二膜。

公开(公告)号：US09456495B2

公开(公告)日：2016-09-27

申请号：US14303317

申请日：2014-06-12

Applicant: Toshihiko Matsumoto ,  Shinichi Komatsu

Inventor： Toshihiko Matsumoto ,  Shinichi Komatsu

IPC: C08G73/10 ,  C07D493/10 ,  C07C69/757 ,  H05K1/03 ,  C07C67/38 ,  C09D179/08 ,  C07C235/82

CPC classification number: H05K1/0346 ,  C07C67/38 ,  C07C69/757 ,  C07C2603/94 ,  C07D493/10 ,  C08G73/105 ,  C08G73/1078 ,  C09D179/08 ,  H05K1/0393 ,  H05K2201/0154 ,  Y10T428/24802

Abstract: A norbornane-2-spiro-α-cycloalkanone-α′-spiro-2″-norbornane-5,5″,6,6″-tetracarboxylic dianhydride represented by the following general formula (1): wherein the formula (1), n represents an integer of 0 to 12, and R1s, R2, R3 each independently represents a hydrogen atom or the like.

公开(公告)号：US09441082B2

公开(公告)日：2016-09-13

申请号：US14583009

申请日：2014-12-24

Applicant: Hisayasu Kaneshiro ,  Toshihisa Itoh ,  Kiyokazu Akahori

Inventor： Hisayasu Kaneshiro ,  Toshihisa Itoh ,  Kiyokazu Akahori

IPC: C08G69/26 ,  C08J5/18 ,  B29C41/28 ,  B29D7/01 ,  B29C41/00 ,  B29C41/24 ,  B29C41/46 ,  C09D179/08 ,  B29K79/00 ,  B29K105/00 ,  B29L7/00

CPC classification number: C08J5/18 ,  B29C41/003 ,  B29C41/24 ,  B29C41/28 ,  B29C41/46 ,  B29D7/01 ,  B29K2079/08 ,  B29K2105/0005 ,  B29K2105/0014 ,  B29L2007/008 ,  C08J2379/08 ,  C09D179/08 ,  H05K2201/0154 ,  Y10T428/31721

Abstract: A process includes the steps of: casting or coating a polyamic acid organic solvent solution on a support and drying the polyamic acid organic solvent solution thereon, so as to form a partially cured and/or partially dried polyamic acid film; dipping the polyamic acid film in tertiary amine or a solution of tertiary amine, or coating tertiary amine or a solution of tertiary amine on the polyamic acid film; and drying the film while imidizing the polyamic acid. In another process, a chemical converting agent and a catalyst are mixed in an organic solvent solution of polyamic acid. After casting and heating the mixture on a support, a partially cured and/or partially dried polyamic acid film is detached from the support. The film contains, with respect to the remaining volatile component, not less than 50 parts of catalyst, not more than 30 parts of solvent, and not more than 20 parts of chemical converting agent and/or a chemical converting agent derived component. The remaining amic acid is imidized and the film is dried.

公开(公告)号：US20160231520A1

公开(公告)日：2016-08-11

申请号：US15029016

申请日：2014-09-11

Applicant: NITTO DENKO CORPORATION

Inventor： Naoki Shibata ,  Yuichi Tsujita

IPC: G02B6/42 ,  H05K1/11

CPC classification number: G02B6/4245 ,  G02B6/42 ,  G02B6/4214 ,  G02B6/4232 ,  G02B6/4239 ,  G02B6/428 ,  H05K1/0274 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/117 ,  H05K3/328 ,  H05K2201/0108 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0191 ,  H05K2201/0358 ,  H05K2201/09481 ,  H05K2201/09827 ,  H05K2201/10121 ,  H05K2201/2009 ,  H05K2201/2054

Abstract: In an opto-electric hybrid board according to the present invention, an electrical interconnect line and an optical element are provided on a first surface of a substrate, and an optical waveguide optically coupled to the optical element is provided on a second surface of the substrate. A reinforcement layer for reinforcing the substrate is integrally mounted on the first surface of the substrate on which the electrical interconnect line and the optical element are provided, with an adhesive layer therebetween. A connector pad part for externally electrically connecting the electrical interconnect line is provided on the second surface of the substrate on which the optical waveguide is provided. With this configuration, the reinforcement layer is mounted on the substrate with high strength without adverse effects exerted on the optical element and the optical waveguide.

Abstract translation: 在根据本发明的光电混合基板中，在基板的第一表面上设置电互连线和光学元件，并且在基板的第二表面上设置光耦合到光学元件的光波导 。 用于加强基板的加强层一体地安装在其上设置有电互连线和光学元件的基板的第一表面上，其间具有粘合剂层。 在其上设置有光波导的基板的第二表面上设置有用于外部电连接电互连线的连接器焊盘部分。 利用这种构造，加强层以高强度安装在基板上，而不会对光学元件和光波导产生不利影响。

公开(公告)号：US09396834B2

公开(公告)日：2016-07-19

申请号：US13814303

申请日：2011-07-29

Applicant: Takashi Syoujiguchi

Inventor： Takashi Syoujiguchi

IPC: H01B3/00 ,  H01B17/62 ,  H05K1/05 ,  H05K3/02 ,  H05K1/03

CPC classification number: H01B3/004 ,  H01B17/62 ,  H05K1/0373 ,  H05K1/05 ,  H05K3/022 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2203/0759 ,  Y10T428/24355 ,  Y10T428/24372

Abstract: A metal foil is provided with a filler-containing resin layer that is thin and has a smooth surface as a metal foil provided with an insulating layer. The filler-containing resin layer having a thickness of 0.1 μm to 3.0 μM, the gloss at the surface of the filler-containing resin layer is 200 or more, and the surface roughness (Ra) measured by an atomic force microscope in a measurement area of 5 μm×5 μM on the filler-containing resin layer is 25 nm or less is stacked on the smooth surface of the metal foil having a gloss exceeding 400 and surface roughness (Ra) measured by an atomic force microscope in a measurement area of 5 μm×5 μm of 10 nm or less.

Abstract translation: 金属箔设置有薄的填充剂树脂层，并且具有作为设置有绝缘层的金属箔的光滑表面。 含有填料的树脂层的厚度为0.1μm〜3.0μm，含填料的树脂层的表面的光泽度为200以上，原子力显微镜在测定区域测定的表面粗糙度（Ra） 在含有填料的树脂层上的5μm×5μM的光泽度在25nm以下层叠在光泽超过400的金属箔的光滑表面上，并且在原子力显微镜的测量区域中测量的表面粗糙度（Ra） 5μm×5μm为10nm以下。