公开(公告)号：US20060097820A1

公开(公告)日：2006-05-11

申请号：US11267754

申请日：2005-11-03

Applicant: Shoji Watanabe ,  Tsutomu Higuchi

Inventor： Shoji Watanabe ,  Tsutomu Higuchi

IPC: H01P5/10

CPC classification number: H05K1/165 ,  H01P5/10 ,  H05K3/0023 ,  H05K3/184 ,  H05K2201/09318

Abstract: A printed circuit board built-in type planar balun which can be easily incorporated in a printed circuit board without increasing the number of layers and lowering the functions thereof is provided. A balanced signal transmission line 1 and an unbalanced signal transmission line 2 are formed on a same plane, with the sides being opposed to each other. Dielectric layers 3 are provided between these transmission lines, and between the transmission line and a ground potential layer 4 which is arranged substantially parallel to the lines 1 and 2 and spaced at a predetermined distance.

Abstract translation: 提供了一种内置式平面平衡 - 不平衡变换器的印刷电路板，其可以容易地结合在印刷电路板中而不增加层数并降低其功能。 平衡信号传输线1和不平衡信号传输线2形成在同一平面上，并且侧面彼此相对。 电介质层3设置在这些传输线之间，传输线和接地电位层4之间，该接地电位层4基本上平行于线路1和2布置并以预定距离隔开。

公开(公告)号：US20050023241A1

公开(公告)日：2005-02-03

申请号：US10917553

申请日：2004-08-11

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01B13/00

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

公开(公告)号：US20040066478A1

公开(公告)日：2004-04-08

申请号：US10263851

申请日：2002-10-03

Applicant: International Business Machines Corporation

Inventor： Donald S. Farquhar ,  Mark D. Poliks

IPC: G02F001/1335

CPC classification number: H05K3/4632 ,  B32B7/04 ,  B32B37/00 ,  B32B37/0046 ,  B32B2037/0092 ,  B32B2305/34 ,  B32B2305/55 ,  B32B2307/204 ,  B32B2307/3065 ,  B32B2307/5825 ,  B32B2309/02 ,  B32B2311/00 ,  C09K19/00 ,  H05K1/0313 ,  H05K3/4641 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/09318 ,  Y10T428/24273 ,  Y10T428/24331

Abstract: A multi-layered structure and method of formation. A page is generated by stacking N substructures (Nnull2) in an ordered sequence. A first substructure of each pair of adjacent substructures comprises liquid crystal polymer (LCP) dielectric material to be bonded with a second substructure of a pair of the adjacent substructure. The page is subjected to a temperature less than the lowest nematic-to-isotropic transition temperature of the LCP dielectric materials within the page. The dwell time and elevated pressure are sufficient to cause all LCP dielectric material within the page to plastically deform and laminate each pair of adjacent substructures without any extrinsic adhesive layer disposed between the first and second substructures of each pair of adjacent substructures.

Abstract translation: 多层结构和形成方法。 通过以有序的顺序堆叠N个子结构（N> = 2）来生成页面。 每对相邻子结构的第一子结构包括要与一对相邻子结构的第二子结构结合的液晶聚合物（LCP）电介质材料。 该页面经受低于页内LCP介电材料的最低向列 - 各向同性转变温度的温度。 停留时间和升高的压力足以使页内的所有LCP电介质材料塑性变形并层压每对相邻的子结构，而不会在每对相邻子结构的第一和第二子结构之间设置任何外在粘合剂层。

公开(公告)号：US20030177638A1

公开(公告)日：2003-09-25

申请号：US10068745

申请日：2002-02-05

Applicant: Force 10 Networks, Inc.

Inventor： Joel R. Goergen

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US06617509B1

公开(公告)日：2003-09-09

申请号：US09495481

申请日：2000-02-01

Applicant: Leif Bergstedt ,  Per Ligander ,  Spartak Gevorgian

Inventor： Leif Bergstedt ,  Per Ligander ,  Spartak Gevorgian

IPC: H01B734

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/09318

Abstract: Method and arrangements for reducing crosstalk between conductors on a conductor carrier, and methods for manufacturing conductor carriers including these arrangements are presented. Crosstalk between the conductors is prevented by providing a dielectric material in the space between each conductor and an earth plane so that the electric field can be tied down within this space and thus prevent leakage of field lines to the co-lateral conductors. The capacitance is increased by an arrangement in the space immediately beneath the conductor so as to reduce the distance between conductors and the earth plane and/or through the medium of a dielectric material that has a higher dielectric index &egr;r than the dielectric material.

Abstract translation: 介绍了减少导体载体上导体之间串扰的方法和装置，以及制造包括这些布置在内的导体载体的方法。 通过在每个导体和接地平面之间的空间中提供介电材料来防止导体之间的串扰，使得电场可以在该空间内被束缚，并且因此防止了场线到同侧导体的泄漏。 通过在导体的正下方的空间中的布置来增加电容，以便减小导体与接地面之间的距离和/或通过介电材料的介质，该介质具有比介电材料更高的介电常数εir。

公开(公告)号：US6061263A

公开(公告)日：2000-05-09

申请号：US221804

申请日：1998-12-29

Applicant: Ted L. Boaz ,  Christopher S. Moore ,  Raviprakash Nagaraj

Inventor： Ted L. Boaz ,  Christopher S. Moore ,  Raviprakash Nagaraj

IPC: G11C5/00 ,  H05K1/02 ,  H05K1/11 ,  G11C7/00

CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  H05K1/0216 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09318 ,  H05K2201/10689

Abstract: A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.

Abstract translation: Rambus在线存储器模块可适用于例如用便携式计算机使用的较小的电路板尺寸。 通过使用错误路由，可以在路由之间匹配阻抗的同时，以小尺寸实现路由。 通过在模块的印刷电路板的一侧上分组信号，并且板的另一侧上的接地和电源触点可以提高性能。

公开(公告)号：US5146674A

公开(公告)日：1992-09-15

申请号：US724245

申请日：1991-07-01

Applicant: Richard F. Frankeny ,  Karl Hermann ,  Ronald L. Imken ,  Joseph LaTorre

Inventor： Richard F. Frankeny ,  Karl Hermann ,  Ronald L. Imken ,  Joseph LaTorre

IPC: H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/20 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H05K3/445 ,  H01L2924/0002 ,  H05K2201/09318 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4641 ,  H05K3/4647 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: Substrate layers with individual bumps and cavities are provided which can be manufactured and tested in parallel and then joined into a multilayer substrate. The method of manufacturing these layers, as contemplated by the present invention, includes initially forming a plurality of vias in a layer of electrically conductive material. Next, a dielectric material, is placed adjacent the layer of conductive material. Holes which are coaxial with the vias are then formed in the dielectric material. Electrically conductive material is then deposited within the vias, thereby forming a conductive stud. Additional electrically conductive material is then deposited, on the side of the dielectric opposite the conductive material to form a signal layer, as well projections of electrically conductive material extending from the studs. A continuous layer of dielectric material is then placed adjacent the side of the substrate opposite the projections. A portion of this layer, adjacent the stud, is then removed, thereby exposing the stud and forming a cavity. The substrate layers can then be joined to form a multilayer substrate module.

Abstract translation: 提供具有单独凸块和空腔的基板层，其可以并联制造和测试，然后连接到多层基板中。 如本发明所设想的制造这些层的方法包括最初在导电材料层中形成多个通孔。 接下来，将电介质材料放置在邻近导电材料层的位置。 然后在电介质材料中形成与通孔同轴的孔。 然后将导电材料沉积在通孔内，从而形成导电柱。 然后在电介质的与导电材料相对的一侧上沉积附加的导电材料以形成信号层，以及从螺柱延伸的导电材料的突起。 然后将连续的介电材料层放置成与衬底相对的与突起相对的一侧。 然后去除邻近螺柱的该层的一部分，从而暴露螺柱并形成空腔。 然后可以将衬底层接合以形成多层衬底模块。

公开(公告)号：US3821610A

公开(公告)日：1974-06-28

申请号：US33617873

申请日：1973-02-27

Applicant: ELECTRONIC CO LTD AB

Inventor： HARCOMBE T

IPC: H04N5/44 ,  H01L27/01 ,  H05K1/02 ,  H05K1/09 ,  H05K1/16 ,  H05K5/00

CPC classification number: H05K1/0237 ,  H01L27/013 ,  H05K1/092 ,  H05K1/167 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663

Abstract: In order to provide screening to prevent unwanted coupling between components on opposite sides of a thick film substrate circuit element, components on one side are located directly opposite printed earth areas of components in the other side.

公开(公告)号：US20170086286A1

公开(公告)日：2017-03-23

申请号：US15364394

申请日：2016-11-30

Applicant: The Boeing Company

Inventor： Robert Tilman Worl

IPC: H05K1/02 ,  H05K3/10 ,  H05K1/03

CPC classification number: H05K1/024 ,  H01P1/00 ,  H05K1/0275 ,  H05K1/0306 ,  H05K3/10 ,  H05K2201/0187 ,  H05K2201/09318 ,  H05K2201/09727 ,  Y10T29/49016 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: An obfuscated radio frequency circuit may be manufactured to include a metallization layer, and a dielectric layer under the metallization layer. The dielectric layer may be made up of a plurality of dielectric substrates having different dielectric constants to obfuscate functions of the circuit.

公开(公告)号：US09515027B2

公开(公告)日：2016-12-06

申请号：US14353185

申请日：2012-12-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Hiroto Tamaki

IPC: H01L23/552 ,  H05K1/02 ,  H01L23/50 ,  H01L23/64

CPC classification number: H01L23/552 ,  H01L23/50 ,  H01L23/642 ,  H01L23/647 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K2201/09318 ,  H01L2924/00

Abstract: A printed circuit board includes a printed circuit board, a semiconductor device mounted on the printed circuit board, a capacitor element mounted on the printed circuit board 2, a ground conductor plane to which a ground terminal of the semiconductor device is connected, and first and second power source conductor planes which are arranged so as not to contact with each other. The second power source conductor plane and the ground conductor plane are arranged so as to oppose to each other to form a planar capacitor. The printed circuit board has a first connecting conductor which connects a power source terminal of the semiconductor device with the second power source conductor plane, and a second connecting conductor which connects the first power source conductor plane with the second power source conductor plane through a first terminal of the capacitor element. Thereby, an electromagnetic radiation noise is reduced.

Abstract translation: 印刷电路板包括印刷电路板，安装在印刷电路板上的半导体器件，安装在印刷电路板2上的电容器元件，连接半导体器件的接地端子的接地导体平面，以及第一和 第二电源导体平面被布置为不彼此接触。 第二电源导体平面和接地导体平面被布置为彼此相对以形成平面电容器。 印刷电路板具有将半导体器件的电源端子与第二电源导体平面连接的第一连接导体和将第一电源导体平面与第二电源导体平面连接的第二连接导体， 端子。 由此，降低了电磁辐射噪声。