公开(公告)号：US20090184778A1

公开(公告)日：2009-07-23

申请号：US12354488

申请日：2009-01-15

Applicant: Kwang-Soo Park ,  Byoung-Ha Oh ,  Yong-Ho Ko

Inventor： Kwang-Soo Park ,  Byoung-Ha Oh ,  Yong-Ho Ko

IPC: H04B15/00

CPC classification number: H05K1/0216 ,  H05K1/0234 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/167 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09318 ,  H05K2201/09327

Abstract: A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.

Abstract translation: 基板包括放置在彼此之间并且基本上彼此平行的电源平面和接地平面以及放置在电源平面和接地平面之间的至少一条信号线。 接地平面包括具有第一导电性的第一导电层。 功率平面包括具有第一导电性的第二导电层，并且功率平面或接地平面包括具有比第一导电率低的第二导电性的第三导电层。 第三导电层面对穿过电介质物质的至少一条信号线。

公开(公告)号：US07502021B2

公开(公告)日：2009-03-10

申请号：US11076784

申请日：2005-03-08

Applicant: Jin-Hyun Choi ,  Kyoung-Soo Lee ,  Sung-Chon Park

Inventor： Jin-Hyun Choi ,  Kyoung-Soo Lee ,  Sung-Chon Park

IPC: G09G5/00

CPC classification number: G09G3/20 ,  G09G2300/023 ,  G09G2300/04 ,  G09G2320/0233 ,  G09G2320/0238 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/0393 ,  H05K2201/09327

Abstract: A stacked structure of a display device is capable of preventing conductive noise due to signal interference by isolating analog and digital output stages and a ground stage onto different layers. A driving device of an organic light emitting display has a scan driver for applying a plurality of scan signals, a data driver for applying a plurality of data signals, and a controller for providing a gradation voltage to the data driver and a scan signal to the scan driver. The stacked structure includes a ground layer, an analog signal-transmission layer for transmitting an analog signal, a digital signal-transmission layer for transmitting a digital signal and a power supply transmission layer for transmitting a power supply voltage. Each of the layers is formed on a different layer. Further, the stacked structure further includes a first mounting layer at a front of the structure on which circuits are mounted and a second mounting layer at a rear thereof on which circuits are mounted. The stacked structure further includes insulating layers formed between the respective layers to insulate the layers.

Abstract translation: 显示装置的堆叠结构能够通过将模拟和数字输出级和接地级隔离到不同的层上来防止由于信号干扰导致的导电噪声。 有机发光显示器的驱动装置具有用于施加多个扫描信号的扫描驱动器，用于施加多个数据信号的数据驱动器，以及用于向数据驱动器提供灰度电压的控制器以及向数据驱动器提供扫描信号 扫描驱动程序 层叠结构包括接地层，用于发送模拟信号的模拟信号传输层，用于发送数字信号的数字信号传输层和用于发送电源电压的电源传输层。 每层都形成在不同的层上。 此外，堆叠结构还包括在其上安装有电路的结构的前部的第一安装层和在其后面安装有电路的第二安装层。 层叠结构还包括形成在各层之间的绝缘层，以使层绝缘。

公开(公告)号：US20080257594A1

公开(公告)日：2008-10-23

申请号：US11812508

申请日：2007-06-19

Applicant: Lars Engblom ,  Mats Johansson ,  Peter Scott

Inventor： Lars Engblom ,  Mats Johansson ,  Peter Scott

IPC: H05K1/18

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09327

Abstract: The present invention relates to a method and a printed board assembly for use in a MicroTCA system, wherein backplane pin connectors of the printed board assembly are arranged to be received in receiving connectors of a backplane interconnect, characterized in that it comprises at least one switch unit which is arranged with physical output/input ports that have physical port numbers that can be overridden by logical port numbers, an optimal routing of a number of sets of conductive threads in the printed board assembly arranged so that none of the conductive threads cross over each other while connecting physical output/input ports of the switch units with the backplane pin connectors, and printed circuit board layers arranged to shield signals travelling in the conductive threads in conductive layers of the printed circuit board layers from any significant crosstalk.

Abstract translation: 本发明涉及一种用于MicroTCA系统的方法和印刷电路板组件，其中印刷电路板组件的背板针连接器被布置成接收在背板互连的接收连接器中，其特征在于，它包括至少一个开关 具有物理输出/输入端口的单元，物理输出/输入端口具有可被逻辑端口号覆盖的物理端口号，布置在印刷电路板组件中的多组导电螺纹的最佳布线，使得没有导电线交叉 彼此相连，同时将开关单元的物理输出/输入端口与背板引脚连接器连接，并且印刷电路板层布置成屏蔽在印刷电路板层的导电层中传导的导电线中的信号免于任何显着的串扰。

公开(公告)号：US07355125B2

公开(公告)日：2008-04-08

申请号：US11281688

申请日：2005-11-17

Applicant: Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

Inventor： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC: H05K1/03

CPC classification number: H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

Abstract: The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure whereina) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, andb) a signal layer being located adjacent to said reference planes.

Abstract translation: 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US20080066951A1

公开(公告)日：2008-03-20

申请号：US11978808

申请日：2007-10-30

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H05K1/02

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises a center segment distributing power and low-speed signaling, and outer segments for high-speed signaling. The segments use dielectric materials with different dielectric constants, with the outer segments supporting higher-speed signal transmission.

Abstract translation: 电路板包括分配功率和低速信号的中心段，以及用于高速信令的外部段。 这些段使用具有不同介电常数的介电材料，外部段支持更高速度的信号传输。

公开(公告)号：US20070217173A1

公开(公告)日：2007-09-20

申请号：US11447866

申请日：2006-06-07

Applicant: Daisuke Mizutani ,  Tatsuhiko Tajima

Inventor： Daisuke Mizutani ,  Tatsuhiko Tajima

IPC: H05K7/00

CPC classification number: H05K9/0016 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09672

Abstract: The circuit board comprises a through-hole via which is formed in a through-hole passed through a substrate and includes a via portion electrically connected to a part of a plurality of interconnection layers at the inside wall of the through-hole and a pad portion formed on a surface of the substrate in a region surrounding the through-hole and is connected to the via portion. In the circuit board, an opening is formed for passing through the through-hole via out of connection with a constant-voltage interconnection layer in the region where the through-holes is formed. The constant-voltage interconnection layer is the interconnection layer nearest to the pad portion, and an outer diameter of the pad portion is larger than a diameter of the opening formed in the constant-voltage interconnection layer, whereby a capacitor including the pad portion and the constant-voltage interconnection layer as a pair of electrodes is formed.

Abstract translation: 电路板包括通孔，该通孔形成在通过基板的通孔中，并且包括通孔部分，电连接到通孔内壁上的多个互连层的一部分，以及焊盘部分 在围绕通孔的区域中形成在基板的表面上并连接到通孔部分。 在电路板中，形成有用于在形成通孔的区域中通过与恒压互连层连接的通孔的开口。 恒压互连层是最靠近焊盘部分的互连层，并且焊盘部分的外径大于形成在恒压互连层中的开口的直径，由此，包括焊盘部分和 形成作为一对电极的恒压互连层。

公开(公告)号：US07057899B2

公开(公告)日：2006-06-06

申请号：US11038460

申请日：2005-01-21

Applicant: Shadi A. AbuGhazaleh ,  Robert C. Baxter ,  Rehan Mahmood ,  Alan C. Miller ,  Michael R. O'Connor

Inventor： Shadi A. AbuGhazaleh ,  Robert C. Baxter ,  Rehan Mahmood ,  Alan C. Miller ,  Michael R. O'Connor

IPC: H05K7/10 ,  H01R24/00

CPC classification number: H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189 ,  H05K2201/10689 ,  Y10S439/941

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 5e, 6 and/or higher (e.g. 6e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.

Abstract translation: 补偿高级功能接线板，其可以包括直接位于接线板上的可拆卸模块或固定电子部件，其分开地或组合地能够提供诸如设备检测和功率插入的高级特征。 接线板提供PD /用户端的绝缘位移连接器（IDC）与使用非屏蔽双绞线电缆的任何标准接口类型之间的通信，例如在开关端的RJ45连接器，性能水平至少为3,5 ，5e，6和/或更高（例如6e或7）和等效的性能水平，通过补偿用于提供高级特征的有源电子元件。 补偿部分通过主动和通信电路元件的分离和隔离来实现。

公开(公告)号：US07045719B1

公开(公告)日：2006-05-16

申请号：US10274573

申请日：2002-10-21

Applicant: Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

Inventor： Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

IPC: H01R12/04

CPC classification number: H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/09327 ,  H05K2201/09718 ,  Y10T29/49165

Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to. In another arrangement, clearances around vias at different power reference plane layers are selected to have different sizes to enhance the ability of one of the power reference plane layers (the one with a smaller clearance size) to carry a higher current level.

Abstract translation: 电路板包括其中信号线路由的多个信号层和功率参考平面层，其中提供功率参考平面（例如，电源电压或地）。 通孔通过至少一个信号层和至少一个功率参考平面层，或者替代地，通孔穿过至少两个功率参考平面层。 在一种布置中，在信号层周围围绕通孔限定第一间隙，并且在功率参考平面层周围的通孔周围限定第二间隙。 第二间隙的尺寸大于第一间隙，以便匹配或调整通孔的阻抗尽可能接近通孔电连接到的信号线的阻抗。 在另一种布置中，选择不同功率参考平面层上的通孔周围的间隙以具有不同的尺寸以增强功率参考平面层（具有较小的间隙尺寸的一个）之一的能力承载更高的电流水平。

公开(公告)号：US20050231124A1

公开(公告)日：2005-10-20

申请号：US11076784

申请日：2005-03-08

Applicant: Jin-Hyun Choi ,  Kyoung-Soo Lee ,  Sung-Chon Park

Inventor： Jin-Hyun Choi ,  Kyoung-Soo Lee ,  Sung-Chon Park

IPC: H05B33/06 ,  G09G3/10 ,  G09G3/20 ,  H05K1/00 ,  H05K1/02

CPC classification number: G09G3/20 ,  G09G2300/023 ,  G09G2300/04 ,  G09G2320/0233 ,  G09G2320/0238 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/0393 ,  H05K2201/09327

Abstract: A stacked structure of a display device is capable of preventing conductive noise due to signal interference by isolating analog and digital output stages and a ground stage onto different layers. A driving device of an organic light emitting display has a scan driver for applying a plurality of scan signals, a data driver for applying a plurality of data signals, and a controller for providing a gradation voltage to the data driver and a scan signal to the scan driver. The stacked structure includes a ground layer, an analog signal-transmission layer for transmitting an analog signal, a digital signal-transmission layer for transmitting a digital signal and a power supply transmission layer for transmitting a power supply voltage. Each of the layers is formed on a different layer. Further, the stacked structure further includes a first mounting layer at a front of the structure on which circuits are mounted and a second mounting layer at a rear thereof on which circuits are mounted. The stacked structure further includes insulating layers formed between the respective layers to insulate the layers.

Abstract translation: 显示装置的堆叠结构能够通过将模拟和数字输出级和接地级隔离到不同的层上来防止由于信号干扰导致的导电噪声。 有机发光显示器的驱动装置具有用于施加多个扫描信号的扫描驱动器，用于施加多个数据信号的数据驱动器，以及用于向数据驱动器提供灰度电压的控制器以及向数据驱动器提供扫描信号 扫描驱动程序 层叠结构包括接地层，用于发送模拟信号的模拟信号传输层，用于发送数字信号的数字信号传输层和用于发送电源电压的电源传输层。 每层都形成在不同的层上。 此外，堆叠结构还包括在其上安装有电路的结构的前部的第一安装层和在其后面安装有电路的第二安装层。 层叠结构还包括形成在各层之间的绝缘层，以使层绝缘。

公开(公告)号：US20050201071A1

公开(公告)日：2005-09-15

申请号：US11038460

申请日：2005-01-21

Applicant: Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

Inventor： Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K7/06

CPC classification number: H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189 ,  H05K2201/10689 ,  Y10S439/941

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 5e, 6 and/or higher (e.g. 6e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.